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    • 6. 发明申请
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20100330758A1
    • 2010-12-30
    • US12656130
    • 2010-01-19
    • Jin-bum KimWook-je KimKwan-heum LeeYu-gyun ShinSun-ghil Lee
    • Jin-bum KimWook-je KimKwan-heum LeeYu-gyun ShinSun-ghil Lee
    • H01L21/8242H01L21/283
    • H01L21/7687H01L27/10855H01L28/91
    • A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.
    • 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层,所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区,形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞,在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层, 通过形成至少一个接触孔,在所述至少一个接触孔中注入离子,以形成所述至少一个埋入接触插塞的非晶体上部,沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上,并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。
    • 7. 发明申请
    • Semiconductor devices and methods of manufacturing the same
    • 半导体器件及其制造方法
    • US20100123198A1
    • 2010-05-20
    • US12591249
    • 2009-11-13
    • Jin-bum KimSi-young ChoiHyung-ik LeeKi-hong KimYong-koo Kyoung
    • Jin-bum KimSi-young ChoiHyung-ik LeeKi-hong KimYong-koo Kyoung
    • H01L27/092H01L21/8238H01L29/772
    • H01L21/823814H01L21/26506H01L21/28518H01L21/28525H01L21/76804H01L21/76814H01L21/76831H01L21/76855H01L21/823871H01L23/485H01L29/165H01L29/665H01L29/6659H01L29/66628H01L29/66636H01L29/7834H01L29/7848H01L2924/0002H01L2924/00
    • Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same. One or more of the semiconductor devices include a substrate having first and second active regions; a P-channel field-effect transistor associated with the first active region and including at least one of the source and drain regions; a N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; a first contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the P-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; a second contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the N-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; an interlayer insulating film formed on the P-channel and the N-channel field-effect transistors and including first and second contact holes, wherein the first contact hole includes a first lower region that exposes the SiGe epitaxial layer of the first contact pad layer and the second contact hole includes a second lower region that penetrates through the SiGe epitaxial layer of the second contact pad layer to expose the Si epitaxial layer of the second contact pad layer; first and second metal silicide films formed respectively in the first and second lower regions of the contact holes; and contact plugs formed on the first and second metal silicide films and filled in the first and second contact holes.
    • 提供具有低电阻触点的半导体器件及其制造方法。 一个或多个半导体器件包括具有第一和第二有源区的衬底; 与所述第一有源区相关并且包括所述源极和漏极区中的至少一个的P沟道场效应晶体管; 与所述第二有源区相关并且包括所述源极和漏极区中的至少一个的N沟道场效应晶体管; 在所述P沟道场效应晶体管的所述源极和漏极区的至少一个上包括硅(Si)和SiGe外延层的第一接触焊盘层,所述SiGe外延层顺序地堆叠在所述Si外延层上; 在所述N沟道场效应晶体管的所述源极和漏极区的至少一个上包括硅(Si)和SiGe外延层的第二接触焊盘层,所述SiGe外延层顺序地堆叠在所述Si外延层上; 形成在P沟道和N沟道场效应晶体管上并且包括第一和第二接触孔的层间绝缘膜,其中第一接触孔包括暴露第一接触焊盘层的SiGe外延层的第一下部区域和 第二接触孔包括穿过第二接触焊盘层的SiGe外延层的第二下部区域,以暴露第二接触焊盘层的Si外延层; 第一和第二金属硅化物膜分别形成在接触孔的第一和第二下部区域中; 以及形成在第一和第二金属硅化物膜上的接触塞,并填充在第一和第二接触孔中。