专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09679977B2 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US09679977B2
公开(公告)日：2017-06-13
申请号：US14861794
申请日：2015-09-22
申请人： Jin-bum Kim , Chul-sung Kim , Deok-han Bae , Bon-young Koo
发明人： Jin-bum Kim , Chul-sung Kim , Deok-han Bae , Bon-young Koo
IPC分类号： H01L29/41 , H01L29/78 , H01L27/092 , H01L21/82 , H01L29/417 , H01L29/66 , H01L29/165 , H01L21/8238
CPC分类号： H01L29/41783 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L27/0924 , H01L29/165 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

2. 发明授权

US10541127B2 Material layers, semiconductor devices including the same, and methods of fabricating material layers and semiconductor devices 有权
公开(公告)号：US10541127B2
公开(公告)日：2020-01-21
申请号：US15336901
申请日：2016-10-28
申请人： Yong-suk Tak , Gi-gwan Park , Jin-bum Kim , Bon-young Koo , Ki-yeon Park , Tae-jong Lee
发明人： Yong-suk Tak , Gi-gwan Park , Jin-bum Kim , Bon-young Koo , Ki-yeon Park , Tae-jong Lee
IPC分类号： H01L21/02 , C23C16/455 , C23C16/50 , H01L21/28 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/786
摘要： A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

3. 发明申请

US20170133219A1 MATERIAL LAYERS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND METHODS OF FABRICATING MATERIAL LAYERS AND SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20170133219A1
公开(公告)日：2017-05-11
申请号：US15336901
申请日：2016-10-28
申请人： Yong-suk Tak , Gi-gwan Park , Jin-bum Kim , Bon-young Koo , Ki-yeon Park , Tae-jong Lee
发明人： Yong-suk Tak , Gi-gwan Park , Jin-bum Kim , Bon-young Koo , Ki-yeon Park , Tae-jong Lee
IPC分类号： H01L21/02 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/16 , C23C16/50 , H01L29/51 , H01L21/28 , H01L29/66 , H01L29/786 , H01L29/423 , C23C16/455 , H01L29/78 , H01L29/49
CPC分类号： H01L21/02126 , C23C16/30 , C23C16/36 , C23C16/45523 , C23C16/45529 , C23C16/45531 , C23C16/45542 , C23C16/50 , H01L21/02211 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/28088 , H01L29/0653 , H01L29/0673 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/42392 , H01L29/4966 , H01L29/4983 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/7854 , H01L29/78618 , H01L29/78651 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

4. 发明申请

US20160027875A1 Semiconductor Devices Having Source/Drain Regions with Strain-Inducing Layers and Methods of Manufacturing Such Semiconductor Devices 有权
标题翻译：具有应变诱导层的源极/漏极区域的半导体器件以及制造这种半导体器件的方法
公开(公告)号：US20160027875A1
公开(公告)日：2016-01-28
申请号：US14680458
申请日：2015-04-07
申请人： Seok-hoon Kim , Jin-bum Kim , Kwan-heum Lee , Byeong-chan Lee , Cho-eun Lee , Su-jin Jung
发明人： Seok-hoon Kim , Jin-bum Kim , Kwan-heum Lee , Byeong-chan Lee , Cho-eun Lee , Su-jin Jung
IPC分类号： H01L29/10 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/02236 , H01L21/02255 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/1033 , H01L29/1054 , H01L29/165 , H01L29/41791 , H01L29/66795 , H01L29/7831 , H01L29/785 , H01L29/7851 , H01L29/7856
摘要： Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.
摘要翻译：半导体器件包括能够对包括在小型化电子器件中的晶体管的沟道区域施加应变的应变诱导层以及半导体器件的制造方法。半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并沿第一方向布置在所述沟道区的两侧; 以及栅极结构，设置在所述沟道区上并且包括在与所述第一方向不同的第二方向上延伸的栅极电极图案，设置在所述沟道区域和所述栅极电极图案之间的栅极介电层以及覆盖相应侧面的栅极间隔件栅电极图案和栅介质层的表面。源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

5. 发明授权

US08324043B2 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers 有权
公开(公告)号：US08324043B2
公开(公告)日：2012-12-04
申请号：US13137733
申请日：2011-09-08
申请人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.

6. 发明申请

US20100330758A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100330758A1
公开(公告)日：2010-12-30
申请号：US12656130
申请日：2010-01-19
申请人： Jin-bum Kim , Wook-je Kim , Kwan-heum Lee , Yu-gyun Shin , Sun-ghil Lee
发明人： Jin-bum Kim , Wook-je Kim , Kwan-heum Lee , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L21/8242 , H01L21/283
CPC分类号： H01L21/7687 , H01L27/10855 , H01L28/91
摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.
摘要翻译：制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层，通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层的所述至少一个埋入式接触插塞。

7. 发明申请

US20100123198A1 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100123198A1
公开(公告)日：2010-05-20
申请号：US12591249
申请日：2009-11-13
申请人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/772
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same. One or more of the semiconductor devices include a substrate having first and second active regions; a P-channel field-effect transistor associated with the first active region and including at least one of the source and drain regions; a N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; a first contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the P-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; a second contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the N-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; an interlayer insulating film formed on the P-channel and the N-channel field-effect transistors and including first and second contact holes, wherein the first contact hole includes a first lower region that exposes the SiGe epitaxial layer of the first contact pad layer and the second contact hole includes a second lower region that penetrates through the SiGe epitaxial layer of the second contact pad layer to expose the Si epitaxial layer of the second contact pad layer; first and second metal silicide films formed respectively in the first and second lower regions of the contact holes; and contact plugs formed on the first and second metal silicide films and filled in the first and second contact holes.
摘要翻译：提供具有低电阻触点的半导体器件及其制造方法。一个或多个半导体器件包括具有第一和第二有源区的衬底; 与所述第一有源区相关并且包括所述源极和漏极区中的至少一个的P沟道场效应晶体管; 与所述第二有源区相关并且包括所述源极和漏极区中的至少一个的N沟道场效应晶体管; 在所述P沟道场效应晶体管的所述源极和漏极区的至少一个上包括硅（Si）和SiGe外延层的第一接触焊盘层，所述SiGe外延层顺序地堆叠在所述Si外延层上; 在所述N沟道场效应晶体管的所述源极和漏极区的至少一个上包括硅（Si）和SiGe外延层的第二接触焊盘层，所述SiGe外延层顺序地堆叠在所述Si外延层上; 形成在P沟道和N沟道场效应晶体管上并且包括第一和第二接触孔的层间绝缘膜，其中第一接触孔包括暴露第一接触焊盘层的SiGe外延层的第一下部区域和第二接触孔包括穿过第二接触焊盘层的SiGe外延层的第二下部区域，以暴露第二接触焊盘层的Si外延层; 第一和第二金属硅化物膜分别形成在接触孔的第一和第二下部区域中; 以及形成在第一和第二金属硅化物膜上的接触塞，并填充在第一和第二接触孔中。

8. 发明授权

US08039902B2 Semiconductor devices having Si and SiGe epitaxial layers 有权
标题翻译：具有Si和SiGe外延层的半导体器件
公开(公告)号：US08039902B2
公开(公告)日：2011-10-18
申请号：US12591249
申请日：2009-11-13
申请人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.
摘要翻译：半导体器件包括具有第一和第二有源区的衬底; 与第一有源区相关并且包括源区和漏区中的至少一个的P沟道晶体管; 与所述第二有源区相关并且包括所述源极和漏极区中的至少一个的N沟道场效应晶体管; 第一和第二接触焊盘层，每个包括在源极和漏极区上的硅（Si）和SiGe外延层，SiGe外延层顺序堆叠在Si外延层上; 层间绝缘膜; 在P沟道晶体管的SiGe外延层上的第一金属硅化物膜和在N沟道晶体管的Si外延层上的第二金属硅化物膜; 以及在第一和第二金属硅化物膜上的接触插塞。

9. 发明申请

US20100197092A1 Method of Manufacturing Semiconductor Device Having Stress Creating Layer 有权
标题翻译：制造具有应力创造层的半导体器件的方法
公开(公告)号：US20100197092A1
公开(公告)日：2010-08-05
申请号：US12693080
申请日：2010-01-25
申请人： Jin-bum Kim , Wook-je Kim , Yu-gyun Shin , Kwan-heum Lee , Sun-Ghil Lee
发明人： Jin-bum Kim , Wook-je Kim , Yu-gyun Shin , Kwan-heum Lee , Sun-Ghil Lee
IPC分类号： H01L21/8238 , H01L21/20
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.
摘要翻译：提供了一种制造具有应力产生层的半导体器件的简化方法。在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区第二区。第一和第二间隔物分别形成在第一和第二栅极的侧壁上。第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。去除第二半导体层。第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

10. 发明授权

US09397219B2 Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices 有权
标题翻译：具有应变诱导层的源极/漏极区域的半导体器件以及制造这种半导体器件的方法
公开(公告)号：US09397219B2
公开(公告)日：2016-07-19
申请号：US14680458
申请日：2015-04-07
申请人： Seok-hoon Kim , Jin-bum Kim , Kwan-heum Lee , Byeong-chan Lee , Cho-eun Lee , Su-jin Jung
发明人： Seok-hoon Kim , Jin-bum Kim , Kwan-heum Lee , Byeong-chan Lee , Cho-eun Lee , Su-jin Jung
IPC分类号： H01L21/302 , H01L21/461 , H01L29/78 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02236 , H01L21/02255 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/1033 , H01L29/1054 , H01L29/165 , H01L29/41791 , H01L29/66795 , H01L29/7831 , H01L29/785 , H01L29/7851 , H01L29/7856
摘要： Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.
摘要翻译：半导体器件包括能够对包括在器件中的晶体管的沟道区域施加应变的应变诱导层以及该器件的制造方法。半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并且沿着第一方向布置在所述沟道区的两侧; 以及设置在通道区域上的栅极结构。栅极结构包括沿与第一方向不同的第二方向延伸的栅极电极图案，沟道区域和栅电极图案之间的栅极介电层以及覆盖栅电极图案的各个侧表面的栅极间隔栅介质层。源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式