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1. 发明授权

US08482049B2 Semiconductor devices and methods for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08482049B2
公开(公告)日：2013-07-09
申请号：US12968389
申请日：2010-12-15
申请人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
发明人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
IPC分类号： H01L29/76
CPC分类号： G11C16/0483 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/66666 , H01L29/7827 , H01L29/7926
摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。多个层间电介质层位于基板上。提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。垂直通道具有内侧壁。在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

2. 发明申请

US20110147824A1 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110147824A1
公开(公告)日：2011-06-23
申请号：US12968389
申请日：2010-12-15
申请人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
发明人： Yong-Hoon Son , Seungjae Baik , Jaehun Jeong , Kihun Hwang
IPC分类号： H01L29/792
CPC分类号： G11C16/0483 , H01L21/28282 , H01L27/11578 , H01L27/11582 , H01L29/66666 , H01L29/7827 , H01L29/7926
摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
摘要翻译：在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。多个层间电介质层位于基板上。提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。垂直通道具有内侧壁。在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

3. 发明申请

US20150333084A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其形成方法
公开(公告)号：US20150333084A1
公开(公告)日：2015-11-19
申请号：US14810845
申请日：2015-07-28
申请人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
发明人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.
摘要翻译：非易失性存储器件包括在衬底上的一串非易失性存储器单元。这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。在衬底中提供连接掺杂半导体区域。该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

4. 发明授权

US08450176B2 Methods of manufacturing rewriteable three-dimensional semiconductor memory devices 有权
标题翻译：制造可重写三维半导体存储器件的方法
公开(公告)号：US08450176B2
公开(公告)日：2013-05-28
申请号：US12968595
申请日：2010-12-15
申请人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
发明人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
IPC分类号： H01L21/336
CPC分类号： H01L21/28 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.
摘要翻译：形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面其中的陷阱密度。该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

5. 发明申请

US20110248327A1 Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same 审中-公开
标题翻译：三维半导体存储器件及其形成方法
公开(公告)号：US20110248327A1
公开(公告)日：2011-10-13
申请号：US13039043
申请日：2011-03-02
申请人： Yong-Hoon Son , Myoungbum Lee , Kihyun Hwang , Seungjae Baik , Jung Ho Kim
发明人： Yong-Hoon Son , Myoungbum Lee , Kihyun Hwang , Seungjae Baik , Jung Ho Kim
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.
摘要翻译：非易失性存储器件包括在衬底上的一串非易失性存储器单元。这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。在衬底中提供连接掺杂半导体区域。该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

6. 发明申请

US20110143524A1 Methods of Manufacturing Rewriteable Three-Dimensional Semiconductor Memory Devices 有权
标题翻译：制造可重写三维半导体存储器件的方法
公开(公告)号：US20110143524A1
公开(公告)日：2011-06-16
申请号：US12968595
申请日：2010-12-15
申请人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
发明人： Yong-Hoon Son , Kihyun Hwang , Seungjae Baik
IPC分类号： H01L21/28 , H01L21/20
CPC分类号： H01L21/28 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.
摘要翻译：形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面其中的陷阱密度。该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

7. 发明授权

US09356033B2 Three-dimensional semiconductor memory devices and methods of forming the same 有权
标题翻译：三维半导体存储器件及其形成方法
公开(公告)号：US09356033B2
公开(公告)日：2016-05-31
申请号：US14810845
申请日：2015-07-28
申请人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
发明人： Yong-Hoon Son , Jung Ho Kim , Seungjae Baik , Myoungbum Lee , Kihyun Hwang
IPC分类号： H01L29/66 , H01L29/78 , H01L27/115
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.
摘要翻译：非易失性存储器件包括在衬底上的一串非易失性存储器单元。这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。在衬底中提供连接掺杂半导体区域。该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

8. 发明授权

US08431984B2 Nonvolatile memory devices including deep and high density trapping layers 有权
标题翻译：非易失性存储器件包括深层和高密度捕获层
公开(公告)号：US08431984B2
公开(公告)日：2013-04-30
申请号：US13035477
申请日：2011-02-25
申请人： Kwangmin Park , Juwan Lim , Seungjae Baik , Siyoung Choi , Kihyun Hwang , Juyul Lee
发明人： Kwangmin Park , Juwan Lim , Seungjae Baik , Siyoung Choi , Kihyun Hwang , Juyul Lee
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/11568 , H01L29/792
摘要： A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer.
摘要翻译：电荷阱非易失性存储器件包括在衬底上的栅电极; 位于栅电极和衬底之间的电荷捕获层，电荷俘获层具有陷阱位置，用于捕获电荷; 捕获层和半导体衬底之间的电荷隧道层; 以及栅电极和俘获层之间的电荷阻挡层。电荷捕获层包括具有多个能量势垒的深陷阱层和具有高于深捕获层的捕获位点密度的捕获位点密度的高密度俘获层。

9. 发明申请

US20100123181A1 NONVOLATILE MEMORY DEVICES INCLUDING MULTIPLE CHARGE TRAPPING LAYERS 有权
标题翻译：非易失性存储器件，包括多个电荷捕获层
公开(公告)号：US20100123181A1
公开(公告)日：2010-05-20
申请号：US12612453
申请日：2009-11-04
申请人： Kwangmin Park , Juwan Lim , Seungjae Baik , Siyoung Choi , Kihyun Hwang , Juyul Lee
发明人： Kwangmin Park , Juwan Lim , Seungjae Baik , Siyoung Choi , Kihyun Hwang , Juyul Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568
摘要： A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer includes a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.
摘要翻译：电荷阱非易失性存储器件包括在衬底上的栅电极; 在基板和栅电极之间的电荷捕获层; 在电荷捕获层和衬底之间的电荷隧道层; 以及栅电极和电荷捕获层之间的电荷阻挡层。电荷捕获层包括具有第一能带隙的第一电荷俘获层和具有不同于第一能带隙的第二能带隙的第二电荷俘获层。第一和第二电荷捕获层被重复堆叠，并且第一和第二能带间隙小于电荷隧穿层和电荷阻挡层的能带隙。

10. 发明授权

US08420482B2 Nonvolatile memory device and method of forming the same 有权
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US08420482B2
公开(公告)日：2013-04-16
申请号：US12458732
申请日：2009-07-21
申请人： Juwan Lim , Sungkweon Baek , Kwangmin Park , Seungjae Baik , Kihyun Hwang
发明人： Juwan Lim , Sungkweon Baek , Kwangmin Park , Seungjae Baik , Kihyun Hwang
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.
摘要翻译：一种非易失性存储器件和一种形成非易失性存储器件的方法，所述方法包括在衬底上形成隧道绝缘层，其中形成隧道绝缘层包括通过以下处理形成多元件绝缘层，所述工艺包括：顺序地提供第一元件源，第二元件源和第三元件源，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成阻挡绝缘层，并在阻挡绝缘层上形成控制栅电极。

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