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1. 发明申请

US20070190723A1 METHOD OF FABRICATING TRANSISTOR OF DRAM SEMICONDUCTOR DEVICE 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US20070190723A1
公开(公告)日：2007-08-16
申请号：US11738620
申请日：2007-04-23
申请人： Yong-Chul OH , Wook-Je KIM , Nak-Jin SON , Se-Myeong JANG , Gyo-Young JIN
发明人： Yong-Chul OH , Wook-Je KIM , Nak-Jin SON , Se-Myeong JANG , Gyo-Young JIN
IPC分类号： H01L21/336
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

2. 发明申请

US20070235785A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070235785A1
公开(公告)日：2007-10-11
申请号：US11697641
申请日：2007-04-06
申请人： Jae-Rok KAHNG , Makoto YOSHIDA , Se-Myeong JANG
发明人： Jae-Rok KAHNG , Makoto YOSHIDA , Se-Myeong JANG
IPC分类号： H01L27/108
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

3. 发明申请

US20160020251A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20160020251A1
公开(公告)日：2016-01-21
申请号：US14724725
申请日：2015-05-28
申请人： Eun-Jung KIM , Se-Myeong JANG , Dae-Ik KIM , Je-Min PARK , Yoo-Sang HWANG
发明人： Eun-Jung KIM , Se-Myeong JANG , Dae-Ik KIM , Je-Min PARK , Yoo-Sang HWANG
IPC分类号： H01L27/22 , H01L43/08 , H01L29/78 , H01L43/02
CPC分类号： H01L27/228 , H01L29/7827 , H01L43/08
摘要： An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other.
摘要翻译： MRAM器件可以包括布置在衬底上的半导体结构，公共源极区，漏极区，沟道区，栅极结构，字线结构，MTJ结构和位线结构。每个半导体结构可以包括具有基本上线性形状的第一半导体图案，该第一半导体图案沿着基本上平行于基板的顶表面的第一方向延伸，以及多个第二图案，每个第二图案沿基本上垂直于基板的第三方向延伸衬底的顶表面。可以在每个半导体结构中形成公共源极区域和漏极区域，以在第三方向上彼此间隔开，并且沟道区域可以布置在公共源极区域和漏极区域之间。可以在相邻的第二半导体图案之间沿第二方向形成栅极结构。字线结构可以将布置在第一方向上的栅极结构彼此电连接。 MTJ结构可以电连接到相应的第二半导体图案。每个位线结构可以将第一方向上的两个相邻的MTJ结构彼此电连接。

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