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1. 发明申请

US20090227106A1 METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20090227106A1
公开(公告)日：2009-09-10
申请号：US12164848
申请日：2008-06-30
申请人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
发明人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
IPC分类号： H01L21/283
CPC分类号： H01L21/76837 , H01L21/76826 , H01L21/76828 , H01L27/10885
摘要： Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10−11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.
摘要翻译：这里公开了一种用于制造半导体存储器件的方法，该半导体存储器件在形成用于隔离位线的层间电介质时可以防止位线的氧化。位线形成在形成下面的结构的半导体衬底上。在形成位线的所得结构上形成介电硅层（SOD）层。可在SOD层上进行热处理，其中在约600℃至约1.5℃范围内的温度范围内，水蒸气（H 2 O）与氢气（H 2）的分压比在约1×10-11至约1.55的范围内，约1100°C

2. 发明申请

US20090111255A1 METHOD FOR FABRICATING TRANSISTOR IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中制作晶体管的方法
公开(公告)号：US20090111255A1
公开(公告)日：2009-04-30
申请号：US12259799
申请日：2008-10-28
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L27/10876
摘要： Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.
摘要翻译：提供了一种在半导体器件中制造晶体管的方法。该方法包括在半导体衬底上形成蚀刻停止层图案; 形成用于覆盖蚀刻停止层图案的半导体层; 形成通过蚀刻所述半导体层图案来暴露所述蚀刻停止层图案的上表面的凹槽; 去除在凹槽中暴露的蚀刻停止层图案; 并形成填充凹槽的栅极。

3. 发明授权

US07851298B2 Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation 有权
标题翻译：在半导体器件中制造晶体管的方法，其利用蚀刻停止层图案作为栅电极形成的虚设图案
公开(公告)号：US07851298B2
公开(公告)日：2010-12-14
申请号：US12259799
申请日：2008-10-28
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hye Jin Seo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66545 , H01L27/10876
摘要： Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.
摘要翻译：提供了一种在半导体器件中制造晶体管的方法。该方法包括在半导体衬底上形成蚀刻停止层图案; 形成用于覆盖蚀刻停止层图案的半导体层; 形成通过蚀刻所述半导体层图案来暴露所述蚀刻停止层图案的上表面的凹槽; 去除在凹槽中暴露的蚀刻停止层图案; 并形成填充凹槽的栅极。

4. 发明授权

US07589012B1 Method for fabricating semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US07589012B1
公开(公告)日：2009-09-15
申请号：US12164848
申请日：2008-06-30
申请人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
发明人： Hye Jin Seo , Yong Seok Eun , Su Ho Kim , An Bae Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76837 , H01L21/76826 , H01L21/76828 , H01L27/10885
摘要： Disclosed herein is a method for fabricating a semiconductor memory device that can prevent oxidation of bit lines when forming an interlayer dielectric for isolating the bit lines. The bit line is formed on a semiconductor substrate where an underlying structure is formed. A silicon on dielectric (SOD) layer is formed on the resulting structure where the bit line is formed. A heat treatment can be performed on the SOD layer with a partial pressure ratio of water vapor (H2O) to hydrogen (H2) in a range of about 1×10−11 to about 1.55 at a temperature in a range of about 600° C. to about 1,100° C.
摘要翻译：这里公开了一种用于制造半导体存储器件的方法，该半导体存储器件在形成用于隔离位线的层间电介质时可以防止位线的氧化。位线形成在形成下面的结构的半导体衬底上。在形成位线的所得结构上形成介电硅层（SOD）层。可在SOD层上进行热处理，其中在约600℃至约1.5℃范围内的温度范围内，水蒸气（H 2 O）与氢气（H 2）的分压比在约1×10-11至约1.55的范围内，约1100°C

5. 发明申请

US20090004816A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090004816A1
公开(公告)日：2009-01-01
申请号：US11949960
申请日：2007-12-04
申请人： An Bae Lee , Yong Seok Eun , Su Ho Kim , Hye Jin Seo
发明人： An Bae Lee , Yong Seok Eun , Su Ho Kim , Hye Jin Seo
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method of forming an isolation layer in a semiconductor device using rapid vapor deposition to fill in a trench of the semiconductor device comprises forming a hydrophilic layer on the trench and forming a hydrophobic layer on a region other than the trench, and selectively forming a buried insulating layer in the trench using a catalytic reaction of the hydrophilic layer.
摘要翻译：在使用快速气相沉积以填充半导体器件的沟槽的半导体器件中形成隔离层的方法包括在沟槽上形成亲水层并在沟槽以外的区域上形成疏水层，并且选择性地形成掩埋使用亲水层的催化反应在沟槽中的绝缘层。

6. 发明授权

US07723189B2 Method for manufacturing semiconductor device having recess gate 失效
标题翻译：具有凹槽的半导体器件的制造方法
公开(公告)号：US07723189B2
公开(公告)日：2010-05-25
申请号：US11618565
申请日：2006-12-29
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L29/66583
摘要： A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.
摘要翻译：一种用于制造具有凹槽的半导体器件的方法包括在半导体衬底上形成蚀刻停止膜; 通过图案化所述蚀刻停止膜形成选择性地暴露所述半导体衬底的蚀刻停止膜图案; 在半导体衬底上形成半导体层; 在半导体衬底上形成用于形成用于凹槽的沟槽的暴露区域的硬掩模膜图案; 使用硬掩模膜图案作为掩模去除半导体层，直到蚀刻停止膜图案被曝光; 通过从半导体衬底去除蚀刻停止膜图案来形成凹槽的沟槽; 以及形成栅极堆叠，每个栅极堆叠形成在用于凹槽的相应的一个沟槽中。

7. 发明申请

US20070259499A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING RECESS GATE 失效
标题翻译：用于制造具有收缩门的半导体器件的方法
公开(公告)号：US20070259499A1
公开(公告)日：2007-11-08
申请号：US11618565
申请日：2006-12-29
申请人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
发明人： Yong Seok Eun , Su Ho Kim , An Bae Lee , Hai Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L29/66583
摘要： A method for manufacturing a semiconductor device having recess gates includes forming an etch stop film on a semiconductor substrate; forming an etch stop film pattern selectively exposing the semiconductor substrate by patterning the etch stop film; forming a semiconductor layer on the semiconductor substrate; forming a hard mask film pattern exposing regions, for forming trenches for recess gates, on the semiconductor substrate; removing the semiconductor layer using the hard mask film pattern as a mask until the etch stop film pattern is exposed; forming the trenches for recess gates by removing the etch stop film pattern from the semiconductor substrate; and forming gate stacks, each of which is formed in the corresponding one of the trenches for recess gates.
摘要翻译：一种用于制造具有凹槽的半导体器件的方法包括在半导体衬底上形成蚀刻停止膜; 通过图案化所述蚀刻停止膜形成选择性地暴露所述半导体衬底的蚀刻停止膜图案; 在半导体衬底上形成半导体层; 在半导体衬底上形成用于形成用于凹槽的沟槽的暴露区域的硬掩模膜图案; 使用硬掩模膜图案作为掩模去除半导体层，直到蚀刻停止膜图案被曝光; 通过从半导体衬底去除蚀刻停止膜图案来形成凹槽的沟槽; 以及形成栅极堆叠，每个栅极堆叠形成在用于凹槽的相应的一个沟槽中。

8. 发明申请

US20080160716A1 METHOD FOR FABRICATING AN ISOLATION LAYER IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于在半导体器件中制造隔离层的方法
公开(公告)号：US20080160716A1
公开(公告)日：2008-07-03
申请号：US11770522
申请日：2007-06-28
申请人： Hye Jin Seo , Eun A. Lee , An Bae Lee
发明人： Hye Jin Seo , Eun A. Lee , An Bae Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76229
摘要： A method for forming an isolation layer in a semiconductor device includes forming a trench inside a semiconductor substrate, forming a fluid insulating layer over the semiconductor substrate, thereby filling the trench with the fluid insulating layer, curing the semiconductor substrate by plasma oxidation to densify the fluid insulating layer, and planarizing the fluid insulating layer to form an isolation layer.
摘要翻译：在半导体器件中形成隔离层的方法包括在半导体衬底内形成沟槽，在半导体衬底上形成流体绝缘层，从而用流体绝缘层填充沟槽，通过等离子体氧化固化半导体衬底，流体绝缘层，并且平坦化流体绝缘层以形成隔离层。

9. 发明授权

US07855113B2 Method for fabricating semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US07855113B2
公开(公告)日：2010-12-21
申请号：US12489019
申请日：2009-06-22
申请人： Yong Soo Joung , Seung Woo Jin , An Bae Lee , Young Hwan Joo
发明人： Yong Soo Joung , Seung Woo Jin , An Bae Lee , Young Hwan Joo
IPC分类号： H01L21/8234
CPC分类号： H01L21/76886 , H01L21/76897 , H01L27/10888 , H01L27/10894
摘要： A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.
摘要翻译：一种制造半导体存储器件的方法包括：在半导体衬底上形成下导电层; 在所述下导电层上形成绝缘层; 蚀刻绝缘层以形成暴露下部导电层的一部分的接触孔; 在接触孔中形成接触塞; 通过在改变半导体衬底的区域的温度的同时执行等离子体掺杂工艺来对接触插塞进行掺杂; 以及通过所述接触插塞形成与所述下导电层连接的上导电层。

10. 发明申请

US20100190326A1 Method for Fabricating Semiconductor Memory Device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20100190326A1
公开(公告)日：2010-07-29
申请号：US12489019
申请日：2009-06-22
申请人： Yong Soo Joung , Seung Woo Jin , An Bae Lee , Young Hwan Joo
发明人： Yong Soo Joung , Seung Woo Jin , An Bae Lee , Young Hwan Joo
IPC分类号： H01L21/28 , H01L21/768
CPC分类号： H01L21/76886 , H01L21/76897 , H01L27/10888 , H01L27/10894
摘要： A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion of the lower conductive layer; forming a contact plug in the contact hole; doping the contact plug by performing a plasma doping process while varying a temperature of regions the semiconductor substrate; and forming an upper conductive layer connected with the lower conductive layer through the contact plug.
摘要翻译：一种制造半导体存储器件的方法包括：在半导体衬底上形成下导电层; 在所述下导电层上形成绝缘层; 蚀刻绝缘层以形成暴露下部导电层的一部分的接触孔; 在接触孔中形成接触塞; 通过在改变半导体衬底的区域的温度的同时执行等离子体掺杂工艺来对接触插塞进行掺杂; 以及通过所述接触插塞形成与所述下导电层连接的上导电层。

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