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1. 发明申请

US20140348299A1 X-RAY IMAGING APPARATUS AND METHOD 审中-公开
标题翻译： X射线成像装置和方法
公开(公告)号：US20140348299A1
公开(公告)日：2014-11-27
申请号：US14006041
申请日：2012-10-30
申请人： Yong Hak Sung , Tae Kyun Kim
发明人： Yong Hak Sung , Tae Kyun Kim
IPC分类号： H05G1/44 , G01T1/29
CPC分类号： H05G1/44 , A61B6/4233 , A61B6/542 , G01T1/2914 , H04N5/23258 , H04N5/32
摘要： The present disclosure provides an X-ray imaging apparatus and method. When capturing an X-ray image using an automatic exposure request signal generated through detection of X-rays emitted from an X-ray generator, the X-ray imaging apparatus and method may verify validity of the automatic exposure request signal, thereby preventing unintentional generation of the automatic exposure request signal due to vibration, temperature change, noise, etc.
摘要翻译：本公开提供了一种X射线成像装置和方法。当使用通过从X射线发生器发射的X射线的检测而产生的自动曝光请求信号来拍摄X射线图像时，X射线成像装置和方法可以验证自动曝光请求信号的有效性，从而防止意外产生由于振动，温度变化，噪音等自动曝光请求信号

2. 发明申请

US20120119357A1 SEMICONDUCTOR APPARATUS 审中-公开
公开(公告)号：US20120119357A1
公开(公告)日：2012-05-17
申请号：US13166118
申请日：2011-06-22
申请人： Sang Jin Byeon , Tae Kyun Kim
发明人： Sang Jin Byeon , Tae Kyun Kim
IPC分类号： H01L23/48 , H01L23/498
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/06 , H01L24/16 , H01L2224/0401 , H01L2224/05553 , H01L2224/05569 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49113 , H01L2225/06544 , H01L2924/00013 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal.
摘要翻译：具有堆叠的第一和第二芯片的半导体装置包括：第一芯片的第一直线，被配置为接收第一编码信号并与第二芯片的第一直线电连接; 所述第一芯片的第二直线被配置为接收第二编码信号; 以及第二芯片的第二直线，被配置为电连接到第一芯片的第一直线并接收第一编码信号。

3. 发明申请

US20100285642A1 Method of Doping Impurity Ions in Dual Gate and Method of Fabricating the Dual Gate using the same 审中-公开
标题翻译：双门掺杂杂质离子的方法及其制作方法
公开(公告)号：US20100285642A1
公开(公告)日：2010-11-11
申请号：US12558215
申请日：2009-09-11
申请人： Kyoung Bong Rouh , Yun Hyuck Ji , Tae Kyun Kim , Woo Sung Kim , Seung Mi Lee
发明人： Kyoung Bong Rouh , Yun Hyuck Ji , Tae Kyun Kim , Woo Sung Kim , Seung Mi Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an upper portion of the gate conductive layer is higher than that in a lower portion; doping second conductivity type impurity ions in a portion of the gate conductive layer in the second region using a mask for opening the portion of the gate conductive layer in the second region; and diffusing the first conductivity type impurity ions and the second conductivity type impurity ions by performing heat treatment.
摘要翻译：在双栅极中掺杂杂质离子的方法包括在具有第一区域和第二区域的半导体衬底上的栅极导电层中掺杂第一导电型杂质离子，其中以浓度梯度进行掺杂，使得掺杂浓度栅极导电层的上部比下部高; 在第二区域中的栅极导电层的一部分中掺杂第二导电型杂质离子，使用掩模，用于在第二区域中打开栅极导电层的部分; 并通过进行热处理使第一导电型杂质离子和第二导电型杂质离子扩散。

4. 发明授权

US07037796B1 Method of manufacturing spacers on sidewalls of titanium polycide gate 失效
标题翻译：在多晶硅化钛栅极的侧壁上制造间隔物的方法
公开(公告)号：US07037796B1
公开(公告)日：2006-05-02
申请号：US09598673
申请日：2000-06-20
申请人： Se Aug Jang , Tae Kyun Kim
发明人： Se Aug Jang , Tae Kyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28061 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the semiconductor device is as follows. There is provided a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed. Herein, the titanium polycide gate is fabricated by an etching step employing the patterned hard mask. Afterward, the substrate is thermal-treated at temperature of 700˜750° C. according to a gate re-oxidation process, thereby forming a re-oxidation layer on side-walls of the gate and on the substrate surface. Next, an oxide layer for spacer is deposited on the resultant at process temperature of 350˜750 C., and a nitride layer is deposited on the oxide layer. Thereafter, a spacer is formed on side-walls of the gate and the hard mask layer by blanket-etching the nitride layer, the oxide layer and the re-oxidation layer.
摘要翻译：公开了半导体器件的制造方法，更具体地说，涉及在多晶硅化钛栅极的侧壁上形成间隔物的方法。半导体器件的制造方法如下。提供了其中顺序地形成栅氧化层，多晶硅层，硅化钛层和图案化硬掩模层的半导体衬底。这里，通过使用图案化硬掩模的蚀刻步骤制造多晶硅化钛栅极。然后，根据栅极再氧化工艺，在700〜750℃的温度下对衬底进行热处理，从而在栅极的侧壁和衬底表面上形成再氧化层。接下来，在350〜750℃的工艺温度下，在所得物上沉积用于间隔物的氧化物层，并且在氧化物层上沉积氮化物层。此后，通过对氮化物层，氧化物层和再氧化层进行毯式蚀刻，在栅极和硬掩模层的侧壁上形成间隔物。

5. 发明授权

US06534352B1 Method for fabricating a MOSFET device 失效
标题翻译：制造MOSFET器件的方法
公开(公告)号：US06534352B1
公开(公告)日：2003-03-18
申请号：US09885083
申请日：2001-06-21
申请人： Tae Kyun Kim
发明人： Tae Kyun Kim
IPC分类号： H01L21336
CPC分类号： H01L29/518 , H01L21/2652 , H01L21/28167 , H01L29/66537 , H01L29/66545 , H01L29/66621
摘要： Disclosed is a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage. The disclosed method relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film. The sacrificial gate structure is then removed to form a groove in the interlayer insulating film that exposes a portion of the silicon substrate. A sacrificial oxide is grown on the exposed silicon substrate and impurity ions are implanted through the oxide to adjust the threshold voltage. The sacrificial oxide is then removed and replaced by a high quality gate insulating film. A metal gate electrode is then formed in the groove above the gate insulating film, thereby forming a MOSFET device having a metal gate.
摘要翻译：公开了一种能够形成超浅结的MOSFET制造方法，同时确保控制阈值电压的稳定性。所公开的方法依赖于使用牺牲栅极结构来形成LDD区域以及添加侧壁间隔物以形成源极/漏极区域，然后沉积层间绝缘膜。然后去除牺牲栅极结构以在层间绝缘膜中形成暴露硅衬底的一部分的凹槽。在暴露的硅衬底上生长牺牲氧化物，并且通过氧化物注入杂质离子以调节阈值电压。然后去除牺牲氧化物并用高质量的栅极绝缘膜代替。然后在栅极绝缘膜上方的沟槽中形成金属栅电极，从而形成具有金属栅极的MOSFET器件。

6. 发明授权

US06417055B2 Method for forming gate electrode for a semiconductor device 有权
标题翻译：用于形成半导体器件的栅电极的方法
公开(公告)号：US06417055B2
公开(公告)日：2002-07-09
申请号：US09895295
申请日：2001-07-02
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L29/665
摘要： The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.
摘要翻译：本发明涉及在接触形成处理中更容忍未对准的半导体器件中形成栅电极的方法。改进的栅极结构减少了栅电极和随后形成的导体（例如DRAM位线和存储线）之间的短路的形成。栅电极由具有相邻绝缘间隔物的镶嵌金属栅电极形成，部分蚀刻金属栅电极以形成沟槽; 沉积氮化物膜; 并蚀刻氮化物膜以在栅电极的外部部分上形成附加的保护绝缘体。通过这些保护绝缘子到位，随后的接触处理变得更加容忍不对准，减少返工和提高产量。

7. 发明授权

US08249851B2 Monitoring system using real-time simulator 有权
标题翻译：使用实时模拟器的监控系统
公开(公告)号：US08249851B2
公开(公告)日：2012-08-21
申请号：US12351525
申请日：2009-01-09
申请人： Su Chul Nam , Jae Gul Lee , Seung Tae Cha , Jeong Hoon Shin , Tae Kyun Kim
发明人： Su Chul Nam , Jae Gul Lee , Seung Tae Cha , Jeong Hoon Shin , Tae Kyun Kim
IPC分类号： G06F17/50
CPC分类号： G01R31/088
摘要： A monitoring system using a real-time simulator, providing a simulation environment of a real electric power system that enables testing of a new electric power system control facility. The operation of the new electric power system control facility and effects thereof on a real electric power system can be evaluated before actual installation. The monitoring system includes a test piece installed in an electric power system; a simulator connected to the test piece, and deriving electric power system simulation data by simulating the electric power system with respect to the test piece; a multimedia interface (MMI) platform interworking with the simulator, providing the simulator with electric power system status data for simulating the electric power system, and receiving the electric power system simulation data from the simulator; and an MMI client interworking with the MMI platform to display the electric power system simulation data from the MMI platform.
摘要翻译：一种使用实时模拟器的监控系统，提供实时电力系统的仿真环境，能够测试新的电力系统控制设施。可以在实际安装之前对新电力系统控制设施的运行及其对真实电力系统的影响进行评估。监控系统包括安装在电力系统中的试件; 连接到试件的模拟器，通过相对于试件模拟电力系统得出电力系统模拟数据; 与模拟器互通的多媒体接口（MMI）平台，为模拟器提供用于模拟电力系统的电力系统状态数据，并从模拟器接收电力系统仿真数据; 以及与MMI平台互通的MMI客户端，以显示MMI平台的电力系统仿真数据。

8. 发明授权

US06946534B2 Fluorinated polyethers having perfluorinated aliphatic group and optical waveguide using the same 失效
标题翻译：具有全氟化脂族基团的氟化聚醚和使用其的光波导
公开(公告)号：US06946534B2
公开(公告)日：2005-09-20
申请号：US09964653
申请日：2001-09-28
申请人： Tae Kyun Kim , Ji Hyang Kim
发明人： Tae Kyun Kim , Ji Hyang Kim
IPC分类号： C08G65/323 , G02B6/12 , G02B6/122 , G02B6/132 , G02B6/136 , C07C41/22
CPC分类号： G02B6/136 , G02B6/1221 , G02B6/132 , G02B2006/12176
摘要： The present invention relates to fluorinated polyethers having a fluorinated aliphatic group at a main chain as represented by the formula (1), as well as a waveguide fabricated using the same: where RF represents OCH2(CF2)nCH2O, or OCH2CF2O(CF2CF2O)nCF2CH2O, where n is a natural number ranging from 1 to 12; Ar1 represents where B is not present or a C═O group, or Ar1 represents where Hal is one selected from F, Cl, Br and I; Ar2 represents where D is one selected from —C(CF3)2, —C(CH3)2, —CO—, —SO2—, —O— and —S—, or Ar2 represents where R1 and R2 are the same or different and each independently represents a halogen atom selected from F, Cl, Br and I, and m is a natural number of 1-3, or Ar2 represents E represents H, or where P is H or a substituted or unsubstituted phenyl group; x is a number ranging from 0.1 to 1.0; y is 1.0−x.
摘要翻译：本发明涉及在式（1）表示的主链上具有氟化脂肪族基团的氟化聚醚，以及使用其制造的波导管，其中R 1表示OCH （CF 2）2 CH 2 O 2或OCH 2 2 CF 2（CH 2）2 CH 2 O（CF 2 CF 2 O）O 2 CF 2 CH 2， SUB> O，其中n是1至12的自然数; Ar 1表示不存在B或C-O基团，或Ar 1表示Hal为选自F，Cl，Br和I中的一个; Ar 2表示其中D是选自-C（CF 3）2）2，-C（CH 3）3，）-SO 2 - ， - CO - ， - SO 2 - ， - O-和-S-或Ar 2表示其中R 1， 1和R 2相同或不同，并且各自独立地表示选自F，Cl，Br和I的卤素原子，m是1-3的自然数，或Ar 2表示E表示H，或其中P为H或取代或未取代的苯基; x为0.1〜1.0的数; y为1.0-x。

9. 发明授权

US08088306B2 Electroconductive thermoplastic resin composition and plastic article including the same 有权
标题翻译：导电热塑性树脂组合物和包含其的塑料制品
公开(公告)号：US08088306B2
公开(公告)日：2012-01-03
申请号：US12488771
申请日：2009-06-22
申请人： Tae Kyun Kim , Young Sil Lee , Young Kyu Chang
发明人： Tae Kyun Kim , Young Sil Lee , Young Kyu Chang
IPC分类号： H01B1/24 , H01B1/22
CPC分类号： C08L101/12 , C08K3/041 , C08K3/22 , C08K2003/2296 , C08L33/08 , C08L69/00
摘要： Disclosed herein are an electrically conductive thermoplastic resin composition and a plastic article including the same. The electrically conductive thermoplastic resin composition comprises about 80 to about 99.9 parts by weight of a thermoplastic resin, about 0.1 to about 10 parts by weight of carbon nanotubes, about 0.1 to about 10 parts by weight of an impact modifier, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes, and about 0.1 to about 10 parts by weight of conductive metal oxide, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes.
摘要翻译：本文公开了导电性热塑性树脂组合物和包含该热塑性树脂组合物的塑料制品。导电热塑性树脂组合物包含约80至约99.9重量份的热塑性树脂，约0.1至约10重量份的碳纳米管，约0.1至约10重量份的抗冲改性剂，基于约100重量份的热塑性树脂和碳纳米管，以及约0.1至约10重量份的导电金属氧化物，基于总共约100重量份的热塑性树脂和碳纳米管。

10. 发明申请

US20110165768A1 Semiconductor Device Having a Modified Recess Channel Gate and a Method for Fabricating the Same 失效
标题翻译：具有改进的凹陷通道门的半导体器件及其制造方法
公开(公告)号：US20110165768A1
公开(公告)日：2011-07-07
申请号：US13046828
申请日：2011-03-14
申请人： Tae Kyun Kim
发明人： Tae Kyun Kim
IPC分类号： H01L21/28
CPC分类号： H01L29/4236 , H01L29/1037 , H01L29/66621
摘要： A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.
摘要翻译：具有修改的凹槽通道栅极的半导体器件包括由器件隔离层限定并且以规则间隔布置在半导体衬底上的有源区，每个有源区在长轴和短轴方向上延伸，在每个有源区中形成沟槽，所述沟槽包括在所述有源区的短轴方向上的阶梯状底面，以及形成在所述沟槽中的凹槽。

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