专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110131031A1 DYNAMIC GENERATION OF TESTS 失效
标题翻译：动态生成测试
公开(公告)号：US20110131031A1
公开(公告)日：2011-06-02
申请号：US12626901
申请日：2009-11-29
申请人： Yoav Avraham Katz , Ron Maharik
发明人： Yoav Avraham Katz , Ron Maharik
IPC分类号： G06F9/44
CPC分类号： G06F11/3684
摘要： Generation of a test based on a test template comprising of branch instructions. The test template may be a layout test template, defining a set of possible control flows possibilities between template instructions in the layout test template. The test is generated by a test generator which may simulate a state of a target computerized system executing the test. The simulation may be performed during generation of the test. The test generator may further verify previously generated instructions. The test generator may further generate instructions associated with leftover template instructions.
摘要翻译：基于包含分支指令的测试模板生成测试。测试模板可以是布局测试模板，在布局测试模板中定义模板指令之间的一组可能的控制流可能性。测试由测试发生器产生，该测试发生器可以模拟执行测试的目标计算机化系统的状态。可以在产生测试期间执行模拟。测试发生器可以进一步验证先前生成的指令。测试发生器还可以产生与剩余模板指令相关联的指令。

2. 发明授权

US08245164B2 Method of verification of address translation mechanisms 有权
标题翻译：地址转换机制验证方法
公开(公告)号：US08245164B2
公开(公告)日：2012-08-14
申请号：US12550419
申请日：2009-08-31
申请人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
发明人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
IPC分类号： G06F17/50
CPC分类号： G06F11/263 , G06F12/10
摘要： Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.
摘要翻译：设备，系统和地址转换机制验证方法。例如，一种用于测试被测设计的地址转换机构的装置，该装置包括：测试发生器，用于接收至少一个地址转换表的规范，并产生一个或多个约束满足问题投影仪在所述地址转换表的多个属性之上。

3. 发明申请

US20120226952A1 AUTOMATIC IDENTIFICATION OF INFORMATION USEFUL FOR GENERATION-BASED FUNCTIONAL VERIFICATION 失效
标题翻译：自动识别有用的基于生成功能验证的信息
公开(公告)号：US20120226952A1
公开(公告)日：2012-09-06
申请号：US13037420
申请日：2011-03-01
申请人： Yoav Avraham Katz , Michal Rimon , Elad Yom-Tov , Avi Ziv
发明人： Yoav Avraham Katz , Michal Rimon , Elad Yom-Tov , Avi Ziv
IPC分类号： G06F11/267
CPC分类号： G06N99/005 , G06F11/261 , G06F11/263
摘要： a computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.
摘要翻译：用于自动提取用于功能验证的有用信息的计算机实现的方法，装置和计算机程序。所述方法包括重复执行操作与被测设计（DUT）相关联的指令生成器，由此确定所生成的指令，所生成的指令具有一个或多个指令属性; 并收集与所生成的指令有关的信息。基于生成的指令和收集的信息，使用分类技术来基于指令属性对信息进行分类。

4. 发明申请

US20080177968A1 RANDOM STIMULI GENERATION OF MEMORY MAPS AND MEMORY ALLOCATIONS 失效
标题翻译：存储器和存储器分配的随机刺激生成
公开(公告)号：US20080177968A1
公开(公告)日：2008-07-24
申请号：US11625831
申请日：2007-01-23
申请人： Roy Emek , Itai Jaeger , Yoav Avraham Katz
发明人： Roy Emek , Itai Jaeger , Yoav Avraham Katz
IPC分类号： G06F12/02
CPC分类号： G06F17/5022
摘要： A computer-implemented method for verification of a hardware design includes specifying requests to allocate regions in a memory of the hardware design, such that at least two of the requests are specified independently of one another. The requests indicate respective allocation types.Overlap restrictions are specified between at least some of the allocation types. The requests and the overlap restrictions are automatically converted to a constraint satisfaction problem (CSP), which includes CSP constraints based on the requests, the allocation types and the overlap restrictions.The CSP is solved to produce a random test program, which includes a memory map that allocates the regions in the memory while complying with the requests and the overlap restrictions. The test program is applied to the hardware design.
摘要翻译：用于验证硬件设计的计算机实现的方法包括指定在硬件设计的存储器中分配区域的请求，使得至少两个请求彼此独立地指定。请求指示相应的分配类型。在至少一些分配类型之间指定重叠限制。请求和重叠限制自动转换为约束满足问题（CSP），其包括基于请求的CSP约束，分配类型和重叠限制。 CSP被解决以产生随机测试程序，其包括在遵守请求和重叠限制的情况下在存储器中分配区域的存储器映射。测试程序适用于硬件设计。

5. 发明授权

US08683282B2 Automatic identification of information useful for generation-based functional verification 失效
标题翻译：自动识别对基于生成的功能验证有用的信息
公开(公告)号：US08683282B2
公开(公告)日：2014-03-25
申请号：US13037420
申请日：2011-03-01
申请人： Yoav Avraham Katz , Michal Rimon , Elad Yom-Tov , Avi Ziv
发明人： Yoav Avraham Katz , Michal Rimon , Elad Yom-Tov , Avi Ziv
IPC分类号： G01R31/28
CPC分类号： G06N99/005 , G06F11/261 , G06F11/263
摘要： A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.
摘要翻译：一种用于自动提取用于功能验证的有用信息的计算机实现的方法，装置和计算机程序。所述方法包括重复执行操作与被测设计（DUT）相关联的指令生成器，由此确定所生成的指令，所生成的指令具有一个或多个指令属性; 并收集与所生成的指令有关的信息。基于生成的指令和收集的信息，使用分类技术来基于指令属性对信息进行分类。

6. 发明申请

US20090319961A1 Method of Verification of Address Translation Mechanisms 有权
标题翻译：地址转换机制验证方法
公开(公告)号：US20090319961A1
公开(公告)日：2009-12-24
申请号：US12550419
申请日：2009-08-31
申请人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
发明人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
IPC分类号： G06F17/50
CPC分类号： G06F11/263 , G06F12/10
摘要： Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.
摘要翻译：设备，系统和地址转换机制验证方法。例如，一种用于测试被测设计的地址转换机构的装置，该装置包括：测试发生器，用于接收至少一个地址转换表的规范，并产生一个或多个约束满足问题投影仪在所述地址转换表的多个属性之上。

7. 发明授权

US07788610B2 Random stimuli generation of memory maps and memory allocations 失效
标题翻译：随机刺激生成内存映射和内存分配
公开(公告)号：US07788610B2
公开(公告)日：2010-08-31
申请号：US11625831
申请日：2007-01-23
申请人： Roy Emek , Itai Jaeger , Yoav Avraham Katz
发明人： Roy Emek , Itai Jaeger , Yoav Avraham Katz
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A computer-implemented method for verification of a hardware design includes specifying requests to allocate regions in a memory of the hardware design, such that at least two of the requests are specified independently of one another. The requests indicate respective allocation types.Overlap restrictions are specified between at least some of the allocation types. The requests and the overlap restrictions are automatically converted to a constraint satisfaction problem (CSP), which includes CSP constraints based on the requests, the allocation types and the overlap restrictions.The CSP is solved to produce a random test program, which includes a memory map that allocates the regions in the memory while complying with the requests and the overlap restrictions. The test program is applied to the hardware design.
摘要翻译：用于验证硬件设计的计算机实现的方法包括指定在硬件设计的存储器中分配区域的请求，使得至少两个请求彼此独立地指定。请求指示相应的分配类型。在至少一些分配类型之间指定重叠限制。请求和重叠限制自动转换为约束满足问题（CSP），其包括基于请求的CSP约束，分配类型和重叠限制。 CSP被解决以产生随机测试程序，其包括在遵守请求和重叠限制的情况下在存储器中分配区域的存储器映射。测试程序适用于硬件设计。

8. 发明申请

US20080209160A1 Device, System and Method of Verification of Address Translation Mechanisms 审中-公开
标题翻译：设备，系统和地址转换机制验证方法
公开(公告)号：US20080209160A1
公开(公告)日：2008-08-28
申请号：US11679192
申请日：2007-02-27
申请人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
发明人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
IPC分类号： G06F12/00
CPC分类号： G06F11/263 , G06F12/10
摘要： Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.
摘要翻译：设备，系统和地址转换机制验证方法。例如，一种用于测试被测设计的地址转换机构的装置，该装置包括：测试发生器，用于接收至少一个地址转换表的规范，并产生一个或多个约束满足问题投影仪在所述地址转换表的多个属性之上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式