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1. 发明授权

US08245164B2 Method of verification of address translation mechanisms 有权
标题翻译：地址转换机制验证方法
公开(公告)号：US08245164B2
公开(公告)日：2012-08-14
申请号：US12550419
申请日：2009-08-31
申请人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
发明人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
IPC分类号： G06F17/50
CPC分类号： G06F11/263 , G06F12/10
摘要： Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.
摘要翻译：设备，系统和地址转换机制验证方法。例如，一种用于测试被测设计的地址转换机构的装置，该装置包括：测试发生器，用于接收至少一个地址转换表的规范，并产生一个或多个约束满足问题投影仪在所述地址转换表的多个属性之上。

2. 发明申请

US20090319961A1 Method of Verification of Address Translation Mechanisms 有权
标题翻译：地址转换机制验证方法
公开(公告)号：US20090319961A1
公开(公告)日：2009-12-24
申请号：US12550419
申请日：2009-08-31
申请人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
发明人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
IPC分类号： G06F17/50
CPC分类号： G06F11/263 , G06F12/10
摘要： Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.
摘要翻译：设备，系统和地址转换机制验证方法。例如，一种用于测试被测设计的地址转换机构的装置，该装置包括：测试发生器，用于接收至少一个地址转换表的规范，并产生一个或多个约束满足问题投影仪在所述地址转换表的多个属性之上。

3. 发明申请

US20080209160A1 Device, System and Method of Verification of Address Translation Mechanisms 审中-公开
标题翻译：设备，系统和地址转换机制验证方法
公开(公告)号：US20080209160A1
公开(公告)日：2008-08-28
申请号：US11679192
申请日：2007-02-27
申请人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
发明人： Yoav Avraham Katz , Anatoly Koyfman , Elena Tsanko
IPC分类号： G06F12/00
CPC分类号： G06F11/263 , G06F12/10
摘要： Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.
摘要翻译：设备，系统和地址转换机制验证方法。例如，一种用于测试被测设计的地址转换机构的装置，该装置包括：测试发生器，用于接收至少一个地址转换表的规范，并产生一个或多个约束满足问题投影仪在所述地址转换表的多个属性之上。

4. 发明授权

US08892386B2 Method and apparatus for post-silicon testing 有权
标题翻译：后硅测试方法和设备
公开(公告)号：US08892386B2
公开(公告)日：2014-11-18
申请号：US13179526
申请日：2011-07-10
申请人： Allon Adir , Eyal Bin , Shady Copty , Anatoly Koyfman , Shimon Landa , Amir Nahir , Vitali Sokhin , Elena Tsanko
发明人： Allon Adir , Eyal Bin , Shady Copty , Anatoly Koyfman , Shimon Landa , Amir Nahir , Vitali Sokhin , Elena Tsanko
IPC分类号： G06F19/00 , G06F11/263
CPC分类号： G06F11/263
摘要： An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.
摘要翻译：一种由计算机化设备执行的装置和计算机实现的方法，包括：生成用于测试一个或多个域的测试数据的集合，其中所述测试数据对于硬件设备的后硅验证是有用的; 根据要测试的硬件设备选择测试数据的集合的子集，以及相对于硬件设备测试的至少一个域; 并索引测试数据集合的子集以获得索引集合。

5. 发明申请

US20130013246A1 METHOD AND APPARATUS FOR POST-SILICON TESTING 有权
标题翻译：后硅测试方法和装置
公开(公告)号：US20130013246A1
公开(公告)日：2013-01-10
申请号：US13179526
申请日：2011-07-10
申请人： Allon Adir , Eyal Bin , Shady Copty , Anatoly Koyfman , Shimon Landa , Amir Nahir , Vitali Sokhin , Elena Tsanko
发明人： Allon Adir , Eyal Bin , Shady Copty , Anatoly Koyfman , Shimon Landa , Amir Nahir , Vitali Sokhin , Elena Tsanko
IPC分类号： H01L21/66 , G06F19/00
CPC分类号： G06F11/263
摘要： An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.
摘要翻译：一种由计算机化设备执行的装置和计算机实现的方法，包括：生成用于测试一个或多个域的测试数据的集合，其中所述测试数据对于硬件设备的后硅验证是有用的; 根据要测试的硬件设备选择测试数据的集合的子集，以及相对于硬件设备测试的至少一个域; 并索引测试数据集合的子集以获得索引集合。

6. 发明授权

US08601418B1 Instruction-by-instruction checking on acceleration platforms 失效
标题翻译：加速平台上的逐个指令检查
公开(公告)号：US08601418B1
公开(公告)日：2013-12-03
申请号：US13471536
申请日：2012-05-15
申请人： Debapriya Chatterjee , Anatoly Koyfman , Ronny Morad , Avi Ziv
发明人： Debapriya Chatterjee , Anatoly Koyfman , Ronny Morad , Avi Ziv
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.
摘要翻译：用于在加速平台上执行逐个指令检查的方法，装置和产品。该方法包括：通过硬件加速器模拟由示踪器模块增强的电路设计上的测试用例的执行，其中在模拟期间，示踪器模块被配置为收集和记录关于通过电路设计完成的关于指令的信息并且关于寄存器值修改; 并将所记录的信息从硬件加速器卸载到计算机化装置，由此，基于卸载的记录信息，计算机化装置可以执行逐个指令检查，每个记录的寄存器修改由在注册修改之前完成。

7. 发明授权

US07370296B2 Modeling language and method for address translation design mechanisms in test generation 有权
标题翻译：测试生成中地址转换设计机制的建模语言和方法
公开(公告)号：US07370296B2
公开(公告)日：2008-05-06
申请号：US10853041
申请日：2004-05-25
申请人： Anatoly Koyfman , Allon Adir , Roy Emek , Yoav Katz , Michael Vinov
发明人： Anatoly Koyfman , Allon Adir , Roy Emek , Yoav Katz , Michael Vinov
IPC分类号： G06F17/50
CPC分类号： G06F11/263 , G06F11/2257
摘要： Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.
摘要翻译：公开了增强测试发生器在处理器设计中自动处理地址转换并且不需要创建特定代码的能力的方法和系统。被测设计的地址转换机制的模型被表示为有向非循环图，然后转换成约束满足问题。这个问题由CSP引擎解决，用于生成用于执行的测试用例的解决方案。使用该模型，测试知识可以传播到适用于许多不同设计的模型，以产生广泛的地址转换机制。

8. 发明申请

US20050278702A1 Modeling language and method for address translation design mechanisms in test generation 有权
标题翻译：测试生成中地址转换设计机制的建模语言和方法
公开(公告)号：US20050278702A1
公开(公告)日：2005-12-15
申请号：US10853041
申请日：2004-05-25
申请人： Anatoly Koyfman , Allon Adir , Roy Emek , Yoav Katz , Michael Vinov
发明人： Anatoly Koyfman , Allon Adir , Roy Emek , Yoav Katz , Michael Vinov
IPC分类号： G06F9/44 , G06F9/45 , G06F11/00 , G06F11/25 , G06F11/263 , G06F17/50 , G06K5/04
CPC分类号： G06F11/263 , G06F11/2257
摘要： Methods and systems are disclosed that enhance the ability of a test generator to automatically deal with address translation in a processor design, and without need for creating specific code. A model of the address translation mechanism of a design-under-test is represented as a directed acyclic graph and then converted into a constraint satisfaction problem. The problem is solved by a CSP engine, and the solution used to generate test cases for execution. Using the model, testing knowledge can be propagated to models applicable to many different designs to produce extensive coverage of address translation mechanisms.
摘要翻译：公开了增强测试发生器在处理器设计中自动处理地址转换并且不需要创建特定代码的能力的方法和系统。被测设计的地址转换机制的模型被表示为有向非循环图，然后转换成约束满足问题。这个问题由CSP引擎解决，用于生成用于执行的测试用例的解决方案。使用该模型，测试知识可以传播到适用于许多不同设计的模型，以产生广泛的地址转换机制。

9. 发明申请

US20130311962A1 INSTRUCTION-BY-INSTRUCTION CHECKING ON ACCELERATION PLATFORMS 失效
标题翻译：通过加速平台进行指导性检查
公开(公告)号：US20130311962A1
公开(公告)日：2013-11-21
申请号：US13471536
申请日：2012-05-15
申请人： Debapriya Chatterjee , Anatoly Koyfman , Ronny Morad , Avi Ziv
发明人： Debapriya Chatterjee , Anatoly Koyfman , Ronny Morad , Avi Ziv
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Method, apparatus and product for performing instruction-by-instruction checking on an acceleration platform. The method comprising: simulating by a hardware accelerator an execution of a testcase on a circuit design enhanced by a tracer module, wherein during the simulation the tracer module is configured to collect and record information regarding instruction which are completed by the circuit design and regarding register value modifications; and off-loading the recorded information from the hardware accelerator to a computerized apparatus, whereby based on the off-loaded recorded information, the computerized apparatus can perform an instruction-by-instruction checking that each recorded register modification is justified by an instruction which is was completed prior to the register modification.
摘要翻译：用于在加速平台上执行逐个指令检查的方法，装置和产品。该方法包括：通过硬件加速器模拟由示踪器模块增强的电路设计上的测试用例的执行，其中在模拟期间，示踪器模块被配置为收集和记录关于通过电路设计完成的和关于寄存器的指令值修改; 并将所记录的信息从硬件加速器卸载到计算机化装置，由此，基于卸载的记录信息，计算机化装置可以执行逐个指令检查，每个记录的寄存器修改由在注册修改之前完成。

10. 发明申请

US20120131386A1 VERIFICATION OF SPECULATIVE EXECUTION 失效
标题翻译：验证执行
公开(公告)号：US20120131386A1
公开(公告)日：2012-05-24
申请号：US12951049
申请日：2010-11-21
申请人： Lurent Fournier , Anatoly Koyfman , Michal Rimon
发明人： Lurent Fournier , Anatoly Koyfman , Michal Rimon
IPC分类号： G06F11/263
CPC分类号： G06F11/263
摘要： A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths.
摘要翻译：设计欠测试（DUT）可以被设计为在确定是否执行分支路径之前执行分支路径的推测执行。公开了DUT对于推测执行的操作的验证。可以使用模板来生成多个测试。除了根据模板对各种参数的测试的标准随机性之外，测试在其各自的推测性执行路径中也可以不同。测试由发生器划分成要放置在投机路径中的部分和要放置在非推测路径中的部分。发电机可以提供部分变化。发生器可以提供嵌套的推测路径。

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