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1. 发明授权

US5754824A Logic synthesis for logic array modules 失效
标题翻译：逻辑阵列模块的逻辑综合
公开(公告)号：US5754824A
公开(公告)日：1998-05-19
申请号：US437918
申请日：1995-05-10
申请人： Robert Damiano , Ilan Yitshak Spillinger , Louise Helen Trevillyan , Lukas Paul Pieter Pepijn Van Ginneken
发明人： Robert Damiano , Ilan Yitshak Spillinger , Louise Helen Trevillyan , Lukas Paul Pieter Pepijn Van Ginneken
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/5054
摘要： A general approach to the synthesis of logic array modules (LAMs) is used to implement a multilevel combinational acyclic network. The network consists of abstract gates, which perform primitive logic functions and nets to connect them. The inputs to the entire network are called the primary inputs and the outputs of the entire network are the primary outputs. The first step in the synthesis of the LAMs used to implement the network is to partition the network vertically to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module. The second step is to partition horizontally the plurality of logic segments to reduce the size of the segments to a size that can efficiently be implemented as a logic array module. A symbolic representation is generated in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments.
摘要翻译：逻辑阵列模块（LAM）的综合方法用于实现多电平组合非循环网络。网络由抽象门组成，执行原始逻辑功能和网络连接。整个网络的输入被称为主要输入，整个网络的输出是主要输出。用于实现网络的LAM的合成的第一步是垂直分割网络以定义多个逻辑段，其中逻辑段的每个输出可潜在地在单个逻辑阵列模块中实现。第二步是水平分割多个逻辑段以将段的大小减小到可以被有效地实现为逻辑阵列模块的大小。在逻辑阵列模块的逻辑阵列模块表中，基于水平分割的逻辑段生成符号表示。

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