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1. 发明申请

US20130140625A1 Field-Effect Transistor and Method of Making 审中-公开
标题翻译：场效应晶体管及制作方法
公开(公告)号：US20130140625A1
公开(公告)日：2013-06-06
申请号：US13642286
申请日：2011-04-25
申请人： Yinghua Piao , Liang Ge , Dongping Wu , Shi-Li Zhang , Wei Zhang
发明人： Yinghua Piao , Liang Ge , Dongping Wu , Shi-Li Zhang , Wei Zhang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L21/26586 , H01L21/823814 , H01L29/0847 , H01L29/66477 , H01L29/66643 , H01L29/66659 , H01L29/7839
摘要： The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor.
摘要翻译：本发明属于微电子器件技术领域。具体地说，公开了非对称源极/漏极场效应晶体管及其制造方法。场效应晶体管的结构包括：半导体衬底，栅极结构，以及分别具有混合结和P-N结的源极区和漏极区。源极区和漏极区彼此不对称地构成，其中之一包括P-N结，另一个包括混合结，该混合结是肖特基结和P-N结的组合。根据本公开，通过调整注入角度来控制通过离子注入形成的掺杂区域的位置，并且为非对称源极/漏极场效应晶体管形成独特的结构。

2. 发明授权

US08697529B2 Schottky junction source/drain transistor and method of making 失效
标题翻译：肖特基结源极/漏极晶体管及其制造方法
公开(公告)号：US08697529B2
公开(公告)日：2014-04-15
申请号：US13508731
申请日：2011-09-28
申请人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/336 , H01L21/338
CPC分类号： H01L29/7839 , H01L29/6653 , H01L29/66848
摘要： A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.
摘要翻译：一种制造晶体管的方法，包括：提供半导体衬底; 在所述半导体衬底上形成栅叠层; 在半导体衬底上形成绝缘层; 在绝缘层上形成耗尽层; 蚀刻耗尽层和绝缘层; 在所述半导体衬底上形成金属层; 进行热退火; 并去除金属层。作为本发明的优点，每个侧壁的上部外侧部分包括能够与金属层反应的材料，从而在退火过程中吸收侧壁两侧的金属，从而防止金属朝向半导体层，并且确保形成的肖特基结可以是超薄和均匀的，并且具有可控和抑制的横向生长。

3. 发明申请

US20130270615A1 METHOD FOR MAKING TRANSISTORS 失效
标题翻译：制造晶体管的方法
公开(公告)号：US20130270615A1
公开(公告)日：2013-10-17
申请号：US13508731
申请日：2011-09-28
申请人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7839 , H01L29/6653 , H01L29/66848
摘要： A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.
摘要翻译：一种制造晶体管的方法，包括：提供半导体衬底; 在所述半导体衬底上形成栅叠层; 在半导体衬底上形成绝缘层; 在绝缘层上形成耗尽层; 蚀刻耗尽层和绝缘层; 在所述半导体衬底上形成金属层; 进行热退火; 并去除金属层。作为本发明的优点，每个侧壁的上部外侧部分包括能够与金属层反应的材料，从而在退火过程中吸收侧壁两侧的金属，从而防止金属朝向半导体层，并且确保形成的肖特基结可以是超薄和均匀的，并且具有可控和抑制的横向生长。

4. 发明申请

US20130295732A1 METHOD FOR MAKING FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制作场效应晶体管的方法
公开(公告)号：US20130295732A1
公开(公告)日：2013-11-07
申请号：US13390328
申请日：2011-09-28
申请人： Dongping Wu , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/2658 , H01L21/324 , H01L29/517 , H01L29/6659
摘要： The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-K gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and PN junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions. The novel process of making a field effect transistor in the present invention can achieve impurity activation in the source/drain area at a low temperature and can reduce the influence of source/drain annealing on high-K gate dielectric and metal gate electrode.
摘要翻译：本发明提供一种制造场效应晶体管的方法，包括以下步骤：提供具有第一类型的硅衬底，通过光刻和蚀刻工艺形成浅沟槽，以及在浅沟槽内形成二氧化硅浅沟槽隔离; 通过在衬底上沉积高K栅介质层和金属栅电极层并形成浅沟槽隔离; 通过光刻和蚀刻工艺形成栅极结构; 通过第二类掺杂剂的离子注入形成源/漏扩展区; 沉积绝缘层以形成紧密地粘附到栅极侧面的侧壁; 通过第二类掺杂剂的离子注入在源极/漏极区域和硅衬底之间形成源极/漏极区域和PN结界面; 并进行微波退火以激活注入的离子。在本发明中制造场效应晶体管的新颖方法可以在低温下在源极/漏极区域实现杂质活化，并且可以减少源极/漏极退火对高K栅极电介质和金属栅电极的影响。

5. 发明授权

US09076730B2 Metal silicide thin film, ultra-shallow junctions, semiconductor device and method of making 有权
标题翻译：金属硅化物薄膜，超浅结，半导体器件及其制造方法
公开(公告)号：US09076730B2
公开(公告)日：2015-07-07
申请号：US13704601
申请日：2012-12-12
申请人： Dongping Wu , Peng Xu , Wei Zhang , Shi-Li Zhang
发明人： Dongping Wu , Peng Xu , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L21/285 , H01L29/66 , H01L29/786 , H01L21/324
CPC分类号： H01L21/28518 , H01L21/2855 , H01L21/324 , H01L29/665 , H01L29/66575 , H01L29/66643 , H01L29/66742 , H01L29/786
摘要： A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.
摘要翻译：公开了一种金属硅化物薄膜和超浅结的制造方法。在本公开中，通过使用金属和半导体掺杂剂混合物作为靶，使用物理气相沉积（PVD）工艺在半导体衬底上形成混合膜。然后通过湿蚀刻除去混合物膜，随后退火以形成金属硅化物薄膜和超浅结。由于金属和半导体掺杂剂混合物用作沉积混合物膜的靶，并且在退火之前通过湿蚀刻除去混合物膜，形成自限制，超薄且均匀的金属硅化物膜和超浅结同时在半导体场效应晶体管制造工艺中，其适用于14nm，11nm甚至更进一步的技术节点处的场效应晶体管。

6. 发明申请

US20140315366A1 Semiconductor Device and Method of Making 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US20140315366A1
公开(公告)日：2014-10-23
申请号：US13704615
申请日：2012-12-14
申请人： Dongping Wu , Chenyu Wen , Wei Zhang , Shi-Li Zhang
发明人： Dongping Wu , Chenyu Wen , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L29/66 , H01L21/768 , H01L21/283
CPC分类号： H01L29/665 , H01L21/283 , H01L21/28518 , H01L21/28525 , H01L21/76802 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.
摘要翻译：本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。在本公开中，晶体管的源极和漏极由在源极和漏极处形成的通孔中形成的金属 - 半导体化合物接触区域和与源极和漏极相对应的通孔中的金属 - 半导体化合物引出。因为金属 - 半导体化合物具有相对低的电阻率，所以可以使过孔中金属 - 半导体化合物的电阻最小化。此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与金属 - 半导体化合物源极/漏极接触区域之间的接触电阻可以被最小化。此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏。因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

7. 发明授权

US09570595B2 Transistor and method of making 有权
标题翻译：晶体管及其制作方法
公开(公告)号：US09570595B2
公开(公告)日：2017-02-14
申请号：US13704613
申请日：2012-12-14
申请人： Dongping Wu , Chaochao Fu , Wei Zhang , Shi-Li Zhang
发明人： Dongping Wu , Chaochao Fu , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L29/737 , H01L29/66 , H01L29/08 , H01L29/10 , H01L21/285 , H01L29/165 , H01L29/167 , H01L29/417 , H01L29/45 , H01L21/02
CPC分类号： H01L29/7378 , H01L21/02532 , H01L21/0257 , H01L21/02598 , H01L21/0262 , H01L21/28518 , H01L21/2855 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/167 , H01L29/41708 , H01L29/456 , H01L29/66242 , H01L29/7371
摘要： A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.
摘要翻译： SiGe HBT具有反相异质结结构，其中发射极层在基极层和集电极层之前形成。 SiGe HBT的频率性能通过基底轮廓的更好的热处理预算得到显着改善，对于较高的截止频率（fT）和减少的寄生电容的最小集电极基极面积是必不可少的，因为较高的最大振荡频率（fmax）。该反转异质结结构可以通过使用ALE工艺在预制的外延硅化物上形成发射极，在发射极上的基极和在基极上的集电极来制造。

8. 发明申请

US20140008604A1 Super-Long Semiconductor Nano-Wire Structure and Method of Making 审中-公开
标题翻译：超长半导体纳米线结构及制作方法
公开(公告)号：US20140008604A1
公开(公告)日：2014-01-09
申请号：US13502110
申请日：2011-09-28
申请人： Dongping Wu , Shi-Li Zhang , Zhiwei Zhu , Wei Zhang
发明人： Dongping Wu , Shi-Li Zhang , Zhiwei Zhu , Wei Zhang
IPC分类号： H01L29/06 , H01L21/308
CPC分类号： H01L29/0669 , B82Y10/00 , B82Y40/00 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L29/122
摘要： The present invention disclosure provides a super-long semiconductor nanowire structure. The super-long semiconductor nanowire structure is intermittently widened to prevent fractures in the super-long semiconductor nanowire structure. At the same time, the present invention further provides a method of making a super-long semiconductor nanowire structure. The method forms an intermittently widened super-long semiconductor nanowire structure using photolithography and etching. Because the super-long semiconductor nanowire structure is intermittently widened, fracturing of the super-long semiconductor nanowire structure during etching can be avoided, making it easier to form a super-long and ultra-thin semiconductor nanowire structure.
摘要翻译：本发明公开了一种超长半导体纳米线结构。超长半导体纳米线结构被间歇地加宽以防止超长半导体纳米线结构中的断裂。同时，本发明还提供了制造超长半导体纳米线结构的方法。该方法使用光刻和蚀刻形成间歇加宽的超长半导体纳米线结构。因为超长半导体纳米线结构被间歇地加宽，所以可以避免在蚀刻过程中超长半导体纳米线结构的断裂，从而更容易形成超长和超薄的半导体纳米线结构。

9. 发明申请

US20130126954A1 Dynamic Random Access Memory Array and Method of Making 审中-公开
标题翻译：动态随机存取存储阵列及其制作方法
公开(公告)号：US20130126954A1
公开(公告)日：2013-05-23
申请号：US13255503
申请日：2011-01-04
申请人： Dongping Wu , Shi-Li Zhang , Peng-Fei Wang , Wei Zhang
发明人： Dongping Wu , Shi-Li Zhang , Peng-Fei Wang , Wei Zhang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10823 , H01L27/1087 , H01L27/10876 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array.
摘要翻译：本发明涉及微电子技术，特别公开了一种动态随机存取存储器（DRAM）阵列及其制造方法。 DRAM阵列使用垂直MOS场效应晶体管作为用于DRAM的阵列器件，并且埋入金属硅化物层作为用于连接多个连续垂直MOS场效应晶体管阵列器件的掩埋位线。每个垂直MOS场效应晶体管阵列器件包括具有金属掩埋层的双栅结构，其与DRAM阵列的掩埋字线同时作用。根据本发明的DRAM阵列提供增加的DRAM集成密度，降低的掩埋位线电阻率和改进的阵列器件的存储器性能。本发明还提供了一种制造DRAM阵列的方法。

10. 发明申请

US20160190293A1 A Transistor and Method of Making 有权
标题翻译：晶体管及其制作方法
公开(公告)号：US20160190293A1
公开(公告)日：2016-06-30
申请号：US13704613
申请日：2012-12-14
申请人： Dongping Wu , Chaochao Fu , Wei Zhang , Shili Zhang
发明人： Dongping Wu , Chaochao Fu , Wei Zhang , Shili Zhang
IPC分类号： H01L29/737 , H01L29/08 , H01L29/165 , H01L21/285 , H01L29/45 , H01L29/417 , H01L29/66 , H01L21/02 , H01L29/10 , H01L29/167
CPC分类号： H01L29/7378 , H01L21/02532 , H01L21/0257 , H01L21/02598 , H01L21/0262 , H01L21/28518 , H01L21/2855 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/167 , H01L29/41708 , H01L29/456 , H01L29/66242 , H01L29/7371
摘要： A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.
摘要翻译： SiGe HBT具有反相异质结结构，其中发射极层在基极层和集电极层之前形成。 SiGe HBT的频率性能通过基底轮廓的更好的热处理预算得到显着改善，对于较高的截止频率（fT）和减少的寄生电容的最小集电极基极面积是必不可少的，因为较高的最大振荡频率（fmax）。该反转异质结结构可以通过使用ALE工艺在预制的外延硅化物上形成发射极，在发射极上的基极和在基极上的集电极来制造。

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