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1. 发明申请

US20130126954A1 Dynamic Random Access Memory Array and Method of Making 审中-公开
标题翻译：动态随机存取存储阵列及其制作方法
公开(公告)号：US20130126954A1
公开(公告)日：2013-05-23
申请号：US13255503
申请日：2011-01-04
申请人： Dongping Wu , Shi-Li Zhang , Peng-Fei Wang , Wei Zhang
发明人： Dongping Wu , Shi-Li Zhang , Peng-Fei Wang , Wei Zhang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10823 , H01L27/1087 , H01L27/10876 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array.
摘要翻译：本发明涉及微电子技术，特别公开了一种动态随机存取存储器（DRAM）阵列及其制造方法。 DRAM阵列使用垂直MOS场效应晶体管作为用于DRAM的阵列器件，并且埋入金属硅化物层作为用于连接多个连续垂直MOS场效应晶体管阵列器件的掩埋位线。每个垂直MOS场效应晶体管阵列器件包括具有金属掩埋层的双栅结构，其与DRAM阵列的掩埋字线同时作用。根据本发明的DRAM阵列提供增加的DRAM集成密度，降低的掩埋位线电阻率和改进的阵列器件的存储器性能。本发明还提供了一种制造DRAM阵列的方法。

2. 发明申请

US20090034355A1 INTEGRATED CIRCUIT INCLUDING MEMORY CELLS WITH TUNNEL FET AS SELECTION TRANSISTOR 审中-公开
标题翻译：集成电路，包括具有隧道FET作为选择晶体管的存储器单元
公开(公告)号：US20090034355A1
公开(公告)日：2009-02-05
申请号：US11830433
申请日：2007-07-30
申请人： Peng-Fei Wang
发明人： Peng-Fei Wang
IPC分类号： G11C8/00 , H01L21/82
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/76 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L29/7391 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： An integrated circuit having an array of memory cells is disclosed. One embodiment provides selection transistors for selecting one of a plurality of memory cells. The selection transistor is a tunnel field effect transistor in order to reduce a leakage current when the transistor is in its non-conducting state. Furthermore an operation method and a method for production are described.
摘要翻译：公开了一种具有存储单元阵列的集成电路。一个实施例提供了用于选择多个存储单元之一的选择晶体管。选择晶体管是隧道场效应晶体管，以便在晶体管处于非导通状态时减小漏电流。此外，描述了操作方法和制造方法。

3. 发明申请

US20070176253A1 Transistor, memory cell and method of manufacturing a transistor 审中-公开
标题翻译：晶体管，存储单元及制造晶体管的方法
公开(公告)号：US20070176253A1
公开(公告)日：2007-08-02
申请号：US11343812
申请日：2006-01-31
申请人： Peng-Fei Wang , Rolf Weis , Joachim Nuetzel , Arnd Scholz , Alexander Sieck , Sigurd Zehner
发明人： Peng-Fei Wang , Rolf Weis , Joachim Nuetzel , Arnd Scholz , Alexander Sieck , Sigurd Zehner
IPC分类号： H01L29/00
CPC分类号： H01L27/10876 , H01L27/10867
摘要： A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.
摘要翻译：公开了一种特别可用于动态随机存取存储器存储单元的存储单元的晶体管，以及制造晶体管的方法。在一个实施例中，晶体管是双鳍场效应晶体管。晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道，用于控制在第一和第二源极/漏极区域之间流动的电流的栅电极。栅极通过栅极电介质与沟道绝缘，其中栅电极设置在在衬底表面中延伸的栅极沟槽中，使得沟道包括在第一和第二源极/漏极区之间延伸的两个鳍状沟道部分垂直于连接第一和第二源极/漏极区域的线截取的截面图，栅极电极在其一侧限定每个鳍状沟道部分。

4. 发明授权

US07795096B2 Method of forming an integrated circuit with two types of transistors 有权
标题翻译：用两种晶体管形成集成电路的方法
公开(公告)号：US07795096B2
公开(公告)日：2010-09-14
申请号：US11647602
申请日：2006-12-29
申请人： Peng-Fei Wang
发明人： Peng-Fei Wang
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823456 , H01L21/823487 , H01L29/4236 , H01L29/66621 , H01L29/7853
摘要： An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.
摘要翻译：集成电路包括具有第一栅电极的第一类型的晶体管和具有第二栅电极的第二类晶体管。第一栅电极形成在限定在半导体衬底中的第一栅极沟槽中，并且第二栅电极形成在限定在半导体衬底中的第二栅极沟槽中。第一栅电极完全填充两个相邻的第一隔离沟槽之间的空间，并且第二栅电极部分地填充两个相邻的第二隔离沟槽之间的空间，衬底部分别分别设置在第二栅极电极和相邻的第二隔离沟槽之间。

5. 发明申请

US20090225580A1 Integrated Circuit, Memory Module, and Method of Manufacturing an Integrated Circuit 审中-公开
标题翻译：集成电路，存储器模块和制造集成电路的方法
公开(公告)号：US20090225580A1
公开(公告)日：2009-09-10
申请号：US12044849
申请日：2008-03-07
申请人： Peng-Fei Wang , Gill Yong Lee , Lothar Risch
发明人： Peng-Fei Wang , Gill Yong Lee , Lothar Risch
IPC分类号： G11C5/06 , H01L21/71
CPC分类号： H01L27/1021 , G11C7/18 , H01L27/101 , H01L27/1022 , H01L27/224 , H01L27/226 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/065 , H01L45/085 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/149
摘要： An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.
摘要翻译：集成电路包括多个存储器单元，每个存储单元包括存储元件和选择器件; 以及连接到存储单元的多个字线和位线。位线，字线和存储元件布置在选择器件上方。

6. 发明申请

US20090173984A1 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路及制造集成电路的方法
公开(公告)号：US20090173984A1
公开(公告)日：2009-07-09
申请号：US11970640
申请日：2008-01-08
申请人： Peng-Fei Wang
发明人： Peng-Fei Wang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/10802 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： The present invention provides an integrated circuit with a floating body transistor comprising two source/drain regions and a floating body region arranged between the two source/drain regions comprising: a back gate electrode separated from the floating body by a first dielectric layer; a control gate electrode, separated from the floating body by a second dielectric layer and overlying the back gate electrode; and a third dielectric layer arranged between the back gate electrode and the control gate electrode. The present invention provides also a method of manufacturing an integrated circuit and a method of operating an integrated circuit.
摘要翻译：本发明提供一种具有浮置体晶体管的集成电路，该浮体晶体管包括两个源极/漏极区域和布置在两个源极/漏极区域之间的浮动体区域，包括：通过第一介电层与浮体隔离的背栅极电极; 控制栅电极，通过第二电介质层与所述浮体隔离并覆盖所述背栅电极; 以及布置在所述背栅电极和所述控制栅电极之间的第三电介质层。本发明还提供一种制造集成电路的方法和操作集成电路的方法。

7. 发明授权

US07442609B2 Method of manufacturing a transistor and a method of forming a memory device with isolation trenches 失效
标题翻译：制造晶体管的方法和形成具有隔离沟槽的存储器件的方法
公开(公告)号：US07442609B2
公开(公告)日：2008-10-28
申请号：US11222613
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Richard Johannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Richard Johannes Luyken
IPC分类号： H01L21/336
CPC分类号： H01L27/10823 , G11C11/404 , H01L21/76897 , H01L27/0207 , H01L27/10826 , H01L27/10829 , H01L27/10867 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.
摘要翻译：一种制造晶体管的方法。在一个实施例中，该方法包括通过在衬底中限定栅极沟槽来形成栅电极。在与沟槽相邻的位置上的每个沟槽中限定了板状部分，使得两个板状部分将与沟槽连接，并且沟槽设置在两个板状部分之间。在一个实施例中，通过蚀刻工艺限定两个板状部分，该蚀刻工艺相对于半导体衬底材料选择性地蚀刻隔离沟槽的隔离材料。栅极绝缘材料设置在有源区域和沟槽之间的界面以及有源区域和板状部分之间的界面处，并且沉积栅电极材料以填充沟槽和两个板状部分。

8. 发明授权

US07429662B2 Red-emitting electrophosphorescent devices 有权
标题翻译：红色发射电致发光器件
公开(公告)号：US07429662B2
公开(公告)日：2008-09-30
申请号：US11133664
申请日：2005-05-20
申请人： Shuit Tong Lee , Chun Sing Lee , Baoxiu Mi , Peng-Fei Wang
发明人： Shuit Tong Lee , Chun Sing Lee , Baoxiu Mi , Peng-Fei Wang
IPC分类号： C07F11/00 , B32B9/00 , B32B19/00
CPC分类号： C09K11/06 , C07F15/0033 , C09K2211/1044 , C09K2211/185 , H01L51/0071 , H01L51/0085 , H01L51/5016 , H05B33/14
摘要： This invention relates to an organic electroluminescence (EL) device and to the use of a tris-cyclometalated iridium complex with a 3-Phenyl-azine ligand for thin-film type organic electroluminescence devices.The iridium complexes used have the following formulae:
摘要翻译：本发明涉及一种有机电致发光（EL）器件，以及三 - 环金属化铱络合物与3-苯基 - 吖嗪配体在薄膜型有机电致发光器件中的应用。所用的铱络合物具有下式：

9. 发明申请

US20080157211A1 Integrated circuit and method of forming the same 有权
标题翻译：集成电路及其形成方法
公开(公告)号：US20080157211A1
公开(公告)日：2008-07-03
申请号：US11647602
申请日：2006-12-29
申请人： Peng-Fei Wang
发明人： Peng-Fei Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823456 , H01L21/823487 , H01L29/4236 , H01L29/66621 , H01L29/7853
摘要： An integrated circuit includes a transistor of a first type with a first gate electrode and a transistor of a second type with a second gate electrode. The first gate electrode is formed in a first gate groove that is defined in a semiconductor substrate, and the second gate electrode is formed in a second gate groove defined in the semiconductor substrate. The first gate electrode completely fills a space between two adjacent first isolation trenches, and the second gate electrode partially fills a space between two adjacent second isolation trenches, with substrate portions being arranged between the second gate electrode and the adjacent second isolation trenches, respectively.
摘要翻译：集成电路包括具有第一栅电极的第一类型的晶体管和具有第二栅电极的第二类晶体管。第一栅电极形成在限定在半导体衬底中的第一栅极沟槽中，并且第二栅电极形成在限定在半导体衬底中的第二栅极沟槽中。第一栅电极完全填充两个相邻的第一隔离沟槽之间的空间，并且第二栅电极部分地填充两个相邻的第二隔离沟槽之间的空间，衬底部分别分别设置在第二栅极电极和相邻的第二隔离沟槽之间。

10. 发明申请

US20070057301A1 Method of manufacturing a transistor, a method of manufacturing a memory device and transistor 失效
标题翻译：制造晶体管的方法，制造存储器件和晶体管的方法
公开(公告)号：US20070057301A1
公开(公告)日：2007-03-15
申请号：US11222540
申请日：2005-09-09
申请人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
发明人： Peng-Fei Wang , Joachim Nuetzel , Rolf Weis , Till Schloesser , Marc Strasser , Hannes Luyken
IPC分类号： H01L29/94
CPC分类号： H01L29/66621 , H01L21/28114 , H01L27/10876 , H01L27/10894 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.
摘要翻译：公开了制造晶体管的方法。该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间口袋栅极绝缘材料设置在有源区域和凹槽之间的界面处以及有源区域和凹穴之间的界面处。沉积栅电极材料以填充凹槽和两个凹穴。

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