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1. 外观设计

USD496035S1 Integrated all-in-one computer 失效
标题翻译：集成多功能一体机
公开(公告)号：USD496035S1
公开(公告)日：2004-09-14
申请号：US29183890
申请日：2003-06-19
申请人： Ying-Chun Chen , Yen-Jen Chen
设计人： Ying-Chun Chen , Yen-Jen Chen

2. 发明申请

US20140049329A1 DIVIDER-LESS PHASE LOCKED LOOP (PLL) 有权
标题翻译：无相位锁相环（PLL）
公开(公告)号：US20140049329A1
公开(公告)日：2014-02-20
申请号：US13586033
申请日：2012-08-15
申请人： Yen-Jen Chen , I-Ting Lee , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh , Shen-Luan Liu
发明人： Yen-Jen Chen , I-Ting Lee , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh , Shen-Luan Liu
IPC分类号： H03L7/099
CPC分类号： H03K3/0322 , H03K3/0315 , H03L7/083 , H03L7/087 , H03L7/089 , H03L7/099
摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
摘要翻译：本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。例如，生成CP信号以分别控制第一CP和第二CP。在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。以这种方式，提供无分频PLL，从而减轻PLL功耗。

3. 发明授权

US07491153B2 Combined exercise management and entertainment unit 有权
标题翻译：组合运动管理和娱乐单位
公开(公告)号：US07491153B2
公开(公告)日：2009-02-17
申请号：US11598637
申请日：2006-11-14
申请人： Chun-Hsing Li , Yen-Jen Chen
发明人： Chun-Hsing Li , Yen-Jen Chen
IPC分类号： A63B21/00
CPC分类号： A63B24/0084 , A63B71/0622 , A63B2071/0625 , A63B2071/0627 , A63B2225/20 , A63B2225/50 , A63B2230/065 , A63B2230/202 , A63B2230/30 , A63B2230/70 , A63B2230/75 , G06F19/00 , G06Q50/22
摘要： A combined exercise management and entertainment unit includes a sensor for sensing a user's body state during exercise and producing an exercise signal to a microprocessor, so as to calculate the user's calorie consumption during exercise each time and the accumulated calorie consumption; a personal characteristics database for storing data of a user's body physical characteristics; an exercise course memory for storing exercise courses set by the user, including the time period, item, and duration of an exercise to be done; a setting unit for the user to set the data of body physical characteristics to be stored in the personal characteristics database; and a play unit having an entertainment information memory for storing a plurality of entertainment information entries, which correspond to the exercise items set by the user and may be selectively played corresponding to the exercise item being done.
摘要翻译：组合的运动管理和娱乐单元包括用于在运动期间感测使用者的身体状态并向微处理器产生运动信号的传感器，以便计算每次运动期间用户的卡路里消耗量和累积卡路里消耗量; 用于存储用户身体物理特征的数据的个人特征数据库; 用于存储用户设置的运动课程的运动课程记忆，包括待完成的锻炼的时间段，项目和持续时间; 设置单元，用于设置要存储在个人特征数据库中的身体物理特性的数据; 以及播放单元，具有娱乐信息存储器，用于存储与用户设置的运动项目相对应的多个娱乐信息条目，并且可以根据正在完成的运动项目选择性地播放。

4. 发明授权

US08890626B2 Divider-less phase locked loop (PLL) 有权
标题翻译：无分频锁相环（PLL）
公开(公告)号：US08890626B2
公开(公告)日：2014-11-18
申请号：US13586033
申请日：2012-08-15
申请人： Yen-Jen Chen , I-Ting Lee , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh , Shen-Iuan Liu
发明人： Yen-Jen Chen , I-Ting Lee , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh , Shen-Iuan Liu
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/0315 , H03L7/083 , H03L7/087 , H03L7/089 , H03L7/099
摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
摘要翻译：本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。例如，生成CP信号以分别控制第一CP和第二CP。在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。以这种方式，提供无分频PLL，从而减轻PLL功耗。

5. 发明授权

US08547151B2 Phase-locked loops that share a loop filter 有权
标题翻译：共享环路滤波器的锁相环路
公开(公告)号：US08547151B2
公开(公告)日：2013-10-01
申请号：US13407394
申请日：2012-02-28
申请人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
发明人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/06 , H03L7/093 , H03L7/099
摘要： A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.
摘要翻译：集成电路的管芯堆叠包括多个管芯。芯片堆叠中的每个裸片包括锁相环（PLL）。每个模具中的PLL共享一个环路滤波器和其他相应的电路。

6. 发明申请

US20060238533A1 Battery power level inspection device co-constructed with system indicators of notebook computer and inspection method thereof 有权
标题翻译：电池功率电平检测装置与笔记本电脑的系统指示器及其检查方法共同构成
公开(公告)号：US20060238533A1
公开(公告)日：2006-10-26
申请号：US11370061
申请日：2006-03-08
申请人： Yen-Jen Chen
发明人： Yen-Jen Chen
IPC分类号： G09G5/00
CPC分类号： G06F1/1616 , G06F1/1684 , G06F1/28
摘要： A notebook computer battery power level inspection device, which is co-constructed with system indicators of the notebook computer, employs an embedded controller of the notebook computer to detect the status of a battery test signal and, in response thereto, generate a signal representing the power level of the battery. Upon detection of the battery test signal, the embedded controller drives individual system indicators of an indicator system of the notebook computer to light or flash for indicating the power level of the battery. The battery test signal is generated by actuating a test switch or by actuating a predetermined one of the keys of a keyboard of the notebook computer.
摘要翻译：与笔记本电脑的系统指示器共同构成的笔记本电脑电池电源电平检查装置采用笔记本电脑的嵌入式控制器来检测电池测试信号的状态，并响应于此产生表示电池的功率电平。在检测到电池测试信号时，嵌入式控制器驱动笔记本计算机的指示器系统的各个系统指示灯亮起或闪烁以指示电池的功率电平。通过启动测试开关或通过致动笔记本计算机的键盘的预定键来产生电池测试信号。

7. 发明授权

US08953730B2 Auto frequency calibration for a phase locked loop and method of use 有权
标题翻译：锁相环的自动频率校准和使用方法
公开(公告)号：US08953730B2
公开(公告)日：2015-02-10
申请号：US13452138
申请日：2012-04-20
申请人： Yen-Jen Chen , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
发明人： Yen-Jen Chen , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/0992 , H03L7/101 , H03L7/103 , H03L7/104 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M3/32
摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.
摘要翻译：锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。锁相环包括配置为接收相位差信号并输出微调信号的数字环路滤波器。锁相环包括配置成接收粗调和微调信号并输出输出频率的压控振荡器。锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

8. 发明申请

US20080082011A1 Computer Input Apparatus with Health Care Function and Health Care Method 审中-公开
标题翻译：具有保健功能和保健方法的计算机输入装置
公开(公告)号：US20080082011A1
公开(公告)日：2008-04-03
申请号：US11532062
申请日：2006-09-14
申请人： Yen-Jen Chen
发明人： Yen-Jen Chen
IPC分类号： A61B5/02
CPC分类号： A61B5/0059 , A61B5/02416 , G06F3/042
摘要： A computer input apparatus with health care function and a health care method are disclosed. The computer input apparatus is connected to a computer through a transmission path. The computer input apparatus comprises at least a light emitting element, an optical track detection module, a measurement module and a transmission control module. A light beam is provided by the light emitting element. The optical track detection module includes a first receiving element for receiving the light beam to detect a displacement signal of the computer input apparatus. The measurement module includes a second receiving element for receiving the light beam to detect a physiology signal of fingertips.
摘要翻译：公开了具有保健功能和保健方法的计算机输入装置。计算机输入装置通过传输路径连接到计算机。计算机输入装置至少包括发光元件，光轨检测模块，测量模块和传输控制模块。由发光元件提供光束。光轨检测模块包括用于接收光束以检测计算机输入装置的位移信号的第一接收元件。测量模块包括用于接收光束以检测指尖的生理信号的第二接收元件。

9. 发明申请

US20070243974A1 Combined exercise management and entertainment unit 有权
标题翻译：组合运动管理和娱乐单位
公开(公告)号：US20070243974A1
公开(公告)日：2007-10-18
申请号：US11598637
申请日：2006-11-14
申请人： Chun-Hsing Li , Yen-Jen Chen
发明人： Chun-Hsing Li , Yen-Jen Chen
IPC分类号： G06Q10/00 , A63B71/00
CPC分类号： A63B24/0084 , A63B71/0622 , A63B2071/0625 , A63B2071/0627 , A63B2225/20 , A63B2225/50 , A63B2230/065 , A63B2230/202 , A63B2230/30 , A63B2230/70 , A63B2230/75 , G06F19/00 , G06Q50/22
摘要： A combined exercise management and entertainment unit includes a sensor for sensing a user's body state during exercise and producing an exercise signal to a microprocessor, so as to calculate the user's calorie consumption during exercise each time and the accumulated calorie consumption; a personal characteristics database for storing data of a user's body physical characteristics; an exercise course memory for storing exercise courses set by the user, including the time period, item, and duration of an exercise to be done; a setting unit for the user to set the data of body physical characteristics to be stored in the personal characteristics database; and a play unit having an entertainment information memory for storing a plurality of entertainment information entries, which correspond to the exercise items set by the user and may be selectively played corresponding to the exercise item being done.
摘要翻译：组合的运动管理和娱乐单元包括用于在运动期间感测使用者的身体状态并向微处理器产生运动信号的传感器，以便计算每次运动期间用户的卡路里消耗量和累积卡路里消耗量; 用于存储用户身体物理特征的数据的个人特征数据库; 用于存储用户设置的运动课程的运动课程记忆，包括待完成的锻炼的时间段，项目和持续时间; 设置单元，用于设置要存储在个人特征数据库中的身体物理特性的数据; 以及播放单元，具有娱乐信息存储器，用于存储与用户设置的运动项目相对应的多个娱乐信息条目，并且可以根据正在完成的运动项目选择性地播放。

10. 发明授权

US08643402B2 Phase frequency detector circuit 有权
标题翻译：相位检波电路
公开(公告)号：US08643402B2
公开(公告)日：2014-02-04
申请号：US13308274
申请日：2011-11-30
申请人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
发明人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D13/00 , H03D3/00
CPC分类号： H03D13/00 , H03D13/004 , H03L7/087 , H03L7/089 , H03L7/10
摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.
摘要翻译：相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。边缘检测器电路被配置为接收第一输入信号和第二输入信号。判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

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