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1. 发明授权

US08953730B2 Auto frequency calibration for a phase locked loop and method of use 有权
标题翻译：锁相环的自动频率校准和使用方法
公开(公告)号：US08953730B2
公开(公告)日：2015-02-10
申请号：US13452138
申请日：2012-04-20
申请人： Yen-Jen Chen , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
发明人： Yen-Jen Chen , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/0992 , H03L7/101 , H03L7/103 , H03L7/104 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M3/32
摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.
摘要翻译：锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。锁相环包括配置为接收相位差信号并输出微调信号的数字环路滤波器。锁相环包括配置成接收粗调和微调信号并输出输出频率的压控振荡器。锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

2. 发明授权

US08643402B2 Phase frequency detector circuit 有权
标题翻译：相位检波电路
公开(公告)号：US08643402B2
公开(公告)日：2014-02-04
申请号：US13308274
申请日：2011-11-30
申请人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
发明人： Yen-Jen Chen , I-Ting Lee , Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou
IPC分类号： H03D13/00 , H03D3/00
CPC分类号： H03D13/00 , H03D13/004 , H03L7/087 , H03L7/089 , H03L7/10
摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.
摘要翻译：相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。边缘检测器电路被配置为接收第一输入信号和第二输入信号。判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

3. 发明授权

US08456207B1 Lock detector and method of detecting lock status for phase lock loop 有权
标题翻译：锁定检测器和检测锁相环锁定状态的方法
公开(公告)号：US08456207B1
公开(公告)日：2013-06-04
申请号：US13297658
申请日：2011-11-16
申请人： Feng Wei Kuo , Kyle Yen , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
发明人： Feng Wei Kuo , Kyle Yen , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
IPC分类号： H03L7/06
CPC分类号： H03L7/095
摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.
摘要翻译：用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。

4. 发明申请

US20130134553A1 INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES 审中-公开
标题翻译：具有噪声抑制特征的插座和半导体封装
公开(公告)号：US20130134553A1
公开(公告)日：2013-05-30
申请号：US13360958
申请日：2012-01-30
申请人： Feng Wei Kuo , Hui Yu Lee , Huan-Neng Chen , Yen-Jen Chen , Yu-Ling Lin , Chewn-Pu Jou
发明人： Feng Wei Kuo , Hui Yu Lee , Huan-Neng Chen , Yen-Jen Chen , Yu-Ling Lin , Chewn-Pu Jou
IPC分类号： H01L29/92 , H01L23/552 , H01L23/498
CPC分类号： H01L23/552 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/642 , H01L23/66 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0655 , H01L2223/6677 , H01L2224/131 , H01L2224/14135 , H01L2224/16225 , H01L2924/14 , H01L2924/1421 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/19042 , H01L2924/19104 , H01L2924/014
摘要： Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
摘要翻译：插入器和半导体封装实施例提供了隔离和抑制电子噪声，例如半导体封装中的EM发射。插入器包括各种实施例中的屏蔽结构，屏蔽结构阻挡来自噪声源的电噪声与其它电信号或装置。在其他实施例中，屏蔽件包括固体结构和一些实施例以及去耦电容器。耦合结构包括多个包含在条中的焊球，其耦合部件并围绕并包含电噪声源。

5. 发明授权

US08547151B2 Phase-locked loops that share a loop filter 有权
标题翻译：共享环路滤波器的锁相环路
公开(公告)号：US08547151B2
公开(公告)日：2013-10-01
申请号：US13407394
申请日：2012-02-28
申请人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
发明人： Feng Wei Kuo , Shyh-An Chi , Huan-Neng Chen , Yen-Jen Chen , Chewn-Pu Jou
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/06 , H03L7/093 , H03L7/099
摘要： A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.
摘要翻译：集成电路的管芯堆叠包括多个管芯。芯片堆叠中的每个裸片包括锁相环（PLL）。每个模具中的PLL共享一个环路滤波器和其他相应的电路。

6. 发明申请

US20140043148A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR WIRELESS INFORMATION ACCESS THEREOF 有权
标题翻译：三维集成电路及其无线信息访问方法
公开(公告)号：US20140043148A1
公开(公告)日：2014-02-13
申请号：US13572533
申请日：2012-08-10
申请人： Mill-Jer WANG , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
发明人： Mill-Jer WANG , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
IPC分类号： G08C17/02 , H01L25/16
CPC分类号： G01R31/2889 , G01R31/3025 , G06F17/5068 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311
摘要： A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure.
摘要翻译：提供了三维集成电路（3DIC）及其无线信息访问方法。所提出的3DIC包括半导体结构和形成在半导体结构上的无线功率器件（WPD），用于无线地接收用于操作从包括探测半导体结构，测试半导体结构和访问第一信息的组中选择的功能的功率从半导体结构。

7. 发明授权

US09275923B2 Band pass filter for 2.5D/3D integrated circuit applications 有权
标题翻译： 2.5D / 3D集成电路应用的带通滤波器
公开(公告)号：US09275923B2
公开(公告)日：2016-03-01
申请号：US13557457
申请日：2012-07-25
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H05K7/00 , H01L21/56 , H01L23/31 , H01L23/64 , H01L23/66 , H01L25/16 , H01L23/00
CPC分类号： H01L23/3128 , H01L23/642 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2223/6627 , H01L2223/6672 , H01L2224/12105 , H01L2224/24195 , H01L2924/181 , H01L2924/19011 , H01L2924/00
摘要： Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.
摘要翻译：一些实施例涉及一种带通滤波器的器件和方法，其具有相对于当前解决方案的降低的成本，面积损失和制造复杂性。集成的无源器件芯片包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片。集成无源器件芯片和收发器芯片也布置在聚合物封装内。超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积的带通滤波器。

8. 发明授权

US09086452B2 Three-dimensional integrated circuit and method for wireless information access thereof 有权
标题翻译：用于无线信息访问的三维集成电路及方法
公开(公告)号：US09086452B2
公开(公告)日：2015-07-21
申请号：US13572533
申请日：2012-08-10
申请人： Mill-Jer Wang , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
发明人： Mill-Jer Wang , Chewn-Pu Jou , Ching-Nen Peng , Huan-Neng Chen , Hung-Chih Lin , Kuang Kai Yen , Hao Chen , Feng Wei Kuo , Ming-Chieh Liu , Tsung-Hsiung Li
IPC分类号： G01R31/28 , H01L23/02 , G06F17/50 , H01L23/00 , H01L25/065 , G01R31/302
CPC分类号： G01R31/2889 , G01R31/3025 , G06F17/5068 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311
摘要： A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure.
摘要翻译：提供了三维集成电路（3DIC）及其无线信息访问方法。所提出的3DIC包括半导体结构和形成在半导体结构上的无线功率器件（WPD），用于无线地接收用于操作从包括探测半导体结构，测试半导体结构和访问第一信息的组中选择的功能的功率从半导体结构。

9. 发明授权

US09275950B2 Bead for 2.5D/3D chip packaging application 有权
标题翻译：珠子用于2.5D / 3D芯片封装应用
公开(公告)号：US09275950B2
公开(公告)日：2016-03-01
申请号：US13481974
申请日：2012-05-29
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
IPC分类号： H01L23/528 , H01L23/552 , H01L23/522
CPC分类号： H01L23/528 , H01L23/5227 , H01L23/552 , H01L2223/6616 , H01L2224/04105 , H01L2224/24137 , H01L2924/14 , H01L2924/15311 , H01L2924/18162
摘要： An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
摘要翻译：具有多层插入器的集成电路封装具有设置在插入件中的一个或多个金属布线珠，所述一个或多个金属布线珠中的每一个具有形成在所述插入件中的所述多层布线结构中的一层中的卷曲布线图案，以及连接到集成电路封装中的电力线的两个终端段，其中所述一个或多个金属布线珠作为功率噪声滤波器起作用。

10. 发明申请

US20140029205A1 Band Pass Filter for 2.5D/3D Integrated Circuit Applications 有权
标题翻译： 2.5D / 3D集成电路应用的带通滤波器
公开(公告)号：US20140029205A1
公开(公告)日：2014-01-30
申请号：US13557457
申请日：2012-07-25
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H05K7/00 , H01L21/56
CPC分类号： H01L23/3128 , H01L23/642 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2223/6627 , H01L2223/6672 , H01L2224/12105 , H01L2224/24195 , H01L2924/181 , H01L2924/19011 , H01L2924/00
摘要： The present disclosure relates to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip comprising a plurality of capacitors embedded in a common molding compound along with a transceiver chip, and arranged within a polymer package. Ultra-thick metallization layers are disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layers also form a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area penalty as compared to conventional solutions. The band pass filter may also be coupled to a plurality of solder balls comprising a Flip Chip Ball Grid Array suitable for 2.5D and 3D integrated circuit applications.
摘要翻译：本公开涉及一种带通滤波器的装置和方法，其具有相对于当前解决方案降低的成本，面积损失和制造复杂性。一种集成的无源器件芯片，包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片，并且布置在聚合物封装内。超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积损失的带通滤波器。带通滤波器还可以耦合到多个焊球，其包括适用于2.5D和3D集成电路应用的倒装芯片球栅阵列。

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