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1. 发明授权

US08605173B2 Differential column ADC architectures for CMOS image sensor applications 有权
标题翻译：用于CMOS图像传感器应用的差分立柱ADC架构
公开(公告)号：US08605173B2
公开(公告)日：2013-12-10
申请号：US12857386
申请日：2010-08-16
申请人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
发明人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
IPC分类号： H04N5/217 , H04N5/76
CPC分类号： H04N5/3575 , H04N5/3742 , H04N5/37455
摘要： Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.
摘要翻译：描述了提供用于高分辨率CMOS图像传感器（CIS）的差分输入，单斜率，列并行模数转换器（ADC）架构的电路，方法和装置。列ADC与像素阵列的列耦合，并且被配置为根据斜坡发生器输出将像素信号电平转换成相应的数字输出值。每个像素被配置为在不同的操作阶段输出像素复位电平和像素信号电平，并且斜坡发生器输出包括在不同操作阶段相同或不同的斜坡复位电平和斜坡信号电平。像素和斜坡输出用于差分驱动列ADC的比较器级，例如降低电源噪声。

2. 发明授权

US08606051B2 Frame-wise calibration of column-parallel ADCs for image sensor array applications 有权
标题翻译：用于图像传感器阵列应用的列并行ADC的逐帧校准
公开(公告)号：US08606051B2
公开(公告)日：2013-12-10
申请号：US12857394
申请日：2010-08-16
申请人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
发明人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
IPC分类号： G06K7/00 , H04N3/14 , H03M1/12 , H03M1/00 , H03M1/34 , H03M1/56
CPC分类号： H04N5/3658 , H03M1/1009 , H03M1/123 , H04N5/378
摘要： Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.
摘要翻译：描述了在图像处理上下文中仅提供每帧（或更少频率）一次的列并行模数转换器（ADC）的校准以减少列逐次噪声的电路，方法和装置。例如，列间ADC在帧间间隔期间进行校准，如垂直消隐间隔。在一些实施例中，用于校准周期的列ADC的校准数据被存储在数字块处，以用于处理来自列ADC的行数据。在其他实施例中，用于校准周期的列ADC的校准数据被存储在本地存储器中的列ADC处，用于在读出数字块进行处理之前对像素数据进行局部校正。在某些实施例中，诸如差分ADC架构的技术被用于在逐帧校准的上下文中减轻行方向噪声。

3. 发明申请

US20120039548A1 FRAME-WISE CALIBRATION OF COLUMN-PARALLEL ADCS FOR IMAGE SENSOR ARRAY APPLICATIONS 有权
标题翻译：用于图像传感器阵列应用的平行平行ADCS的框架校正
公开(公告)号：US20120039548A1
公开(公告)日：2012-02-16
申请号：US12857394
申请日：2010-08-16
申请人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
发明人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
IPC分类号： G06K9/20
CPC分类号： H04N5/3658 , H03M1/1009 , H03M1/123 , H04N5/378
摘要： Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.
摘要翻译：描述了在图像处理上下文中仅提供每帧（或更少频率）一次的列并行模数转换器（ADC）的校准以减少列逐次噪声的电路，方法和装置。例如，列间ADC在帧间间隔期间进行校准，如垂直消隐间隔。在一些实施例中，用于校准周期的列ADC的校准数据被存储在数字块处，以用于处理来自列ADC的行数据。在其他实施例中，用于校准周期的列ADC的校准数据被存储在本地存储器中的列ADC处，用于在读出数字块进行处理之前对像素数据进行局部校正。在某些实施例中，诸如差分ADC架构的技术被用于在逐帧校准的上下文中减轻行方向噪声。

4. 发明申请

US20120038809A1 DIFFERENTIAL COLUMN ADC ARCHITECTURES FOR CMOS IMAGE SENSOR APPLICATIONS 有权
标题翻译： CMOS图像传感器应用的差分ADC架构
公开(公告)号：US20120038809A1
公开(公告)日：2012-02-16
申请号：US12857386
申请日：2010-08-16
申请人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
发明人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
IPC分类号： H04N5/335
CPC分类号： H04N5/3575 , H04N5/3742 , H04N5/37455
摘要： Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.
摘要翻译：描述了提供用于高分辨率CMOS图像传感器（CIS）的差分输入，单斜率，列并行模数转换器（ADC）架构的电路，方法和装置。列ADC与像素阵列的列耦合，并且被配置为根据斜坡发生器输出将像素信号电平转换成相应的数字输出值。每个像素被配置为在不同的操作阶段输出像素复位电平和像素信号电平，并且斜坡发生器输出包括在不同操作阶段相同或不同的斜坡复位电平和斜坡信号电平。像素和斜坡输出用于差分驱动列ADC的比较器级，例如降低电源噪声。

5. 发明申请

US20120169909A1 IMAGE PROCESSING SYSTEM WITH ON-CHIP TEST MODE FOR COLUMN ADCS 有权
标题翻译：具有片上测试模式的图像处理系统
公开(公告)号：US20120169909A1
公开(公告)日：2012-07-05
申请号：US12981970
申请日：2010-12-30
申请人： Jeff RYSINSKI , Yibing Michelle Wang , Sang-Soo Lee
发明人： Jeff RYSINSKI , Yibing Michelle Wang , Sang-Soo Lee
IPC分类号： H04N5/335
CPC分类号： H04N5/374 , H03M1/1033 , H03M1/123 , H03M1/56 , H04N5/378 , H04N17/002
摘要： An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.
摘要翻译：图像处理系统包括：像素阵列，包括多个规则像素列和至少一个测试像素列;多个列模数转换器（ADC），被配置为对应于规则像素列并将模拟输入信号转换成数字信号和切换块，被配置为提供常规像素列的输出信号以在正常模式下输入相应的列ADC的端部，并且共同提供测试像素列的输出信号到列ADC的输入端在测试模式中，其中测试像素列产生具有不同于一行至另一行的微小电压的信号。

6. 发明授权

US08823850B2 Image processing system with on-chip test mode for column ADCs 有权
标题翻译：具有片内ADC测试模式的图像处理系统
公开(公告)号：US08823850B2
公开(公告)日：2014-09-02
申请号：US12981970
申请日：2010-12-30
申请人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
发明人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
IPC分类号： H04N5/335 , H03M1/10 , H04N5/228 , H04N17/00 , H04N5/378 , H04N5/374 , H03M1/56 , H03M1/12
CPC分类号： H04N5/374 , H03M1/1033 , H03M1/123 , H03M1/56 , H04N5/378 , H04N17/002
摘要： An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.
摘要翻译：图像处理系统包括：像素阵列，包括多个规则像素列和至少一个测试像素列;多个列模数转换器（ADC），被配置为对应于规则像素列并将模拟输入信号转换成数字信号和切换块，被配置为提供常规像素列的输出信号以在正常模式下输入相应的列ADC的端部，并且共同提供测试像素列的输出信号到列ADC的输入端在测试模式中，其中测试像素列产生具有不同于一行至另一行的微小电压的信号。

7. 发明授权

US08390486B2 Automatic offset adjustment for digital calibration of column parallel single-slope ADCs for image sensors 有权
标题翻译：用于图像传感器的列并行单斜率ADC的数字校准的自动偏移调整
公开(公告)号：US08390486B2
公开(公告)日：2013-03-05
申请号：US13118991
申请日：2011-05-31
申请人： Yibing Michelle Wang , Jeff Rysinski , Hongyu Wang , Sang-Soo Lee
发明人： Yibing Michelle Wang , Jeff Rysinski , Hongyu Wang , Sang-Soo Lee
IPC分类号： H03M1/06
CPC分类号： H03M1/1019 , H03M1/123 , H03M1/56 , H04N5/365 , H04N5/378
摘要： Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.
摘要翻译：本发明的各种实施例包括在校准阶段期间使计数器能够计数小于与所确定的偏移量相关联的数个时钟周期的数量。计数的时钟周期数存储在校准存储器中。在转换阶段，反相输出从校准存储器加载到计数器，其中计数器被使能以对时钟周期进行计数以确定模拟信号幅度的数字等效值。

8. 发明授权

US08988111B2 Cascoded comparator with dynamic biasing for column parallel single slope ADCs 有权
标题翻译：具有串并联单斜率ADC的动态偏置的Cascoded比较器
公开(公告)号：US08988111B2
公开(公告)日：2015-03-24
申请号：US13017839
申请日：2011-01-31
申请人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
发明人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
IPC分类号： H03K19/00 , H03K19/02 , H03F3/45 , H03K5/24 , H03M1/12 , H03M1/56
CPC分类号： H03K5/2472 , H03F3/45188 , H03F2203/45292 , H03F2203/45302 , H03F2203/45674 , H03K5/2481 , H03M1/12 , H03M1/123 , H03M1/36 , H03M1/56
摘要： Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.
摘要翻译：本发明的方面可以包括经由相应的第一和第二输入晶体管接收第一输入信号和第二输入信号。由共源共栅偏压发生器产生的偏置信号跟踪第一输入信号，其中偏置信号相对于第一输入信号具有固定的偏移。偏置信号可以分别施加到可以级联到第一和第二输入晶体管的第一和第二共源共栅晶体管。

9. 发明授权

US08368570B2 Method and system for calibrating column parallel ADCs 有权
标题翻译：校准列并行ADC的方法和系统
公开(公告)号：US08368570B2
公开(公告)日：2013-02-05
申请号：US13018165
申请日：2011-01-31
申请人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
发明人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
IPC分类号： H03M1/06
CPC分类号： H03M1/1019 , H03M1/123 , H03M1/56
摘要： Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.
摘要翻译：本发明的各种实施例包括在校准阶段期间允许计数器计数一个小于与所确定的偏移相关联的数个时钟周期。计数的时钟周期数存储在校准存储器中。在转换阶段，反相输出从校准存储器加载到计数器，其中计数器被使能以对时钟周期进行计数以确定模拟信号幅度的数字等效值。

10. 发明申请

US20140079401A1 WAVELENGTH-DIVISION MULTIPLEXING OPTICAL COMMUNICATION SYSTEM AND METHOD FOR MEASURING OPTICAL PERFORMANCE OF AN OUTPUT SIGNAL FOR THE SYSTEM 有权
标题翻译：波长多路复用光通信系统及测量系统输出信号光学性能的方法
公开(公告)号：US20140079401A1
公开(公告)日：2014-03-20
申请号：US14118922
申请日：2012-05-25
申请人： Han-Hyub Lee , Jie-Hyun Lee , Eon-Sang Kim , Sang-Soo Lee
发明人： Han-Hyub Lee , Jie-Hyun Lee , Eon-Sang Kim , Sang-Soo Lee
IPC分类号： H04B10/079 , H04J14/02
CPC分类号： H04J14/0242 , H04B10/0795 , H04B10/2587 , H04J14/02 , H04J2014/0253
摘要： A wavelength-division multiplexing optical communication system and a method for measuring optical performance of an output signal for the system. The optical communication system includes: a service-provider device; a local node; and a plurality of subscriber devices. The service-provider device includes: a plurality of first optical transceivers; a first optical multiplexer/demultiplexer (OD/OM) connected to the plurality of first optical transceivers; and a seed-light source providing seed light. Each subscriber device includes a second optical transceiver. The local node connects the service-provider device and the plurality of subscriber devices to each other using a DWDM link comprising: a second multiplexer/demultiplexer (OD/OM); and a single-mode optical fiber for transmission. Here, the optical intensity of an output signal of the second optical transceiver is determined by compensating for the value of the loss caused when the output signal passes through the second OD/OM of the local node.
摘要翻译：一种波分复用光通信系统和用于测量该系统的输出信号的光学性能的方法。光通信系统包括：服务提供者设备; 一个本地节点; 和多个订户设备。服务提供者设备包括：多个第一光收发器; 连接到所述多个第一光收发器的第一光复用器/解复用器（OD / OM）; 和提供种子光的种子光源。每个用户设备包括第二光收发器。本地节点使用DWDM链路将服务提供商设备和多个用户设备彼此连接，包括：第二多路复用器/解复用器（OD / OM）; 和用于传输的单模光纤。这里，通过补偿当输出信号通过本地节点的第二OD / OM时引起的损耗的值来确定第二光收发器的输出信号的光强度。

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