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1. 发明授权

US08605173B2 Differential column ADC architectures for CMOS image sensor applications 有权
标题翻译：用于CMOS图像传感器应用的差分立柱ADC架构
公开(公告)号：US08605173B2
公开(公告)日：2013-12-10
申请号：US12857386
申请日：2010-08-16
申请人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
发明人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
IPC分类号： H04N5/217 , H04N5/76
CPC分类号： H04N5/3575 , H04N5/3742 , H04N5/37455
摘要： Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.
摘要翻译：描述了提供用于高分辨率CMOS图像传感器（CIS）的差分输入，单斜率，列并行模数转换器（ADC）架构的电路，方法和装置。列ADC与像素阵列的列耦合，并且被配置为根据斜坡发生器输出将像素信号电平转换成相应的数字输出值。每个像素被配置为在不同的操作阶段输出像素复位电平和像素信号电平，并且斜坡发生器输出包括在不同操作阶段相同或不同的斜坡复位电平和斜坡信号电平。像素和斜坡输出用于差分驱动列ADC的比较器级，例如降低电源噪声。

2. 发明授权

US08606051B2 Frame-wise calibration of column-parallel ADCs for image sensor array applications 有权
标题翻译：用于图像传感器阵列应用的列并行ADC的逐帧校准
公开(公告)号：US08606051B2
公开(公告)日：2013-12-10
申请号：US12857394
申请日：2010-08-16
申请人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
发明人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
IPC分类号： G06K7/00 , H04N3/14 , H03M1/12 , H03M1/00 , H03M1/34 , H03M1/56
CPC分类号： H04N5/3658 , H03M1/1009 , H03M1/123 , H04N5/378
摘要： Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.
摘要翻译：描述了在图像处理上下文中仅提供每帧（或更少频率）一次的列并行模数转换器（ADC）的校准以减少列逐次噪声的电路，方法和装置。例如，列间ADC在帧间间隔期间进行校准，如垂直消隐间隔。在一些实施例中，用于校准周期的列ADC的校准数据被存储在数字块处，以用于处理来自列ADC的行数据。在其他实施例中，用于校准周期的列ADC的校准数据被存储在本地存储器中的列ADC处，用于在读出数字块进行处理之前对像素数据进行局部校正。在某些实施例中，诸如差分ADC架构的技术被用于在逐帧校准的上下文中减轻行方向噪声。

3. 发明申请

US20120039548A1 FRAME-WISE CALIBRATION OF COLUMN-PARALLEL ADCS FOR IMAGE SENSOR ARRAY APPLICATIONS 有权
标题翻译：用于图像传感器阵列应用的平行平行ADCS的框架校正
公开(公告)号：US20120039548A1
公开(公告)日：2012-02-16
申请号：US12857394
申请日：2010-08-16
申请人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
发明人： Yibing Michelle Wang , Jeffrey Joseph Rysinski , Sang-Soo Lee
IPC分类号： G06K9/20
CPC分类号： H04N5/3658 , H03M1/1009 , H03M1/123 , H04N5/378
摘要： Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.
摘要翻译：描述了在图像处理上下文中仅提供每帧（或更少频率）一次的列并行模数转换器（ADC）的校准以减少列逐次噪声的电路，方法和装置。例如，列间ADC在帧间间隔期间进行校准，如垂直消隐间隔。在一些实施例中，用于校准周期的列ADC的校准数据被存储在数字块处，以用于处理来自列ADC的行数据。在其他实施例中，用于校准周期的列ADC的校准数据被存储在本地存储器中的列ADC处，用于在读出数字块进行处理之前对像素数据进行局部校正。在某些实施例中，诸如差分ADC架构的技术被用于在逐帧校准的上下文中减轻行方向噪声。

4. 发明申请

US20120038809A1 DIFFERENTIAL COLUMN ADC ARCHITECTURES FOR CMOS IMAGE SENSOR APPLICATIONS 有权
标题翻译： CMOS图像传感器应用的差分ADC架构
公开(公告)号：US20120038809A1
公开(公告)日：2012-02-16
申请号：US12857386
申请日：2010-08-16
申请人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
发明人： Sang-Soo Lee , Yibing Michelle Wang , Jeffrey Joseph Rysinski
IPC分类号： H04N5/335
CPC分类号： H04N5/3575 , H04N5/3742 , H04N5/37455
摘要： Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.
摘要翻译：描述了提供用于高分辨率CMOS图像传感器（CIS）的差分输入，单斜率，列并行模数转换器（ADC）架构的电路，方法和装置。列ADC与像素阵列的列耦合，并且被配置为根据斜坡发生器输出将像素信号电平转换成相应的数字输出值。每个像素被配置为在不同的操作阶段输出像素复位电平和像素信号电平，并且斜坡发生器输出包括在不同操作阶段相同或不同的斜坡复位电平和斜坡信号电平。像素和斜坡输出用于差分驱动列ADC的比较器级，例如降低电源噪声。

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