专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09880596B2 Power management mechanism 有权
公开(公告)号：US09880596B2
公开(公告)日：2018-01-30
申请号：US13536819
申请日：2012-06-28
申请人： Hank Cheng , Bharath Upputuri
发明人： Hank Cheng , Bharath Upputuri
IPC分类号： G11B17/028 , G06F1/26 , G06F1/28 , H02M3/335 , G11C7/12
CPC分类号： G06F1/26 , G06F1/28 , G11C7/12 , H02M3/335 , Y10T307/406
摘要： An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

2. 发明授权

US08315119B2 Sense amplifier scheme for low voltage SRAM and register files 有权
标题翻译：用于低电压SRAM和寄存器文件的感应放大器方案
公开(公告)号：US08315119B2
公开(公告)日：2012-11-20
申请号：US12684842
申请日：2010-01-08
申请人： Bharath Upputuri
发明人： Bharath Upputuri
IPC分类号： G11C7/02
CPC分类号： G11C11/419 , G11C7/067 , G11C11/413 , G11C11/418
摘要： A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output.
摘要翻译：公开了一种用于SRAM的读出放大器方案。根据本申请的一个实施例，读出放大器电路包括位线，读出放大器输出，具有电源电压的电源节点，包括NMOS晶体管的保持电路和噪声阈值控制电路。保持器电路的尺寸设置为提供足够的电流以补偿位线的漏电流并维持位线的电压电平，并且噪声阈值控制电路降低读出放大器输出的跳变点。

3. 发明授权

US08630134B2 Memory cells having a row-based read and/or write support circuitry 有权
标题翻译：存储单元具有基于行的读和/或写支持电路
公开(公告)号：US08630134B2
公开(公告)日：2014-01-14
申请号：US13489055
申请日：2012-06-05
申请人： Shreekanth Sampigethaya , Bharath Upputuri
发明人： Shreekanth Sampigethaya , Bharath Upputuri
IPC分类号： G11C7/02
CPC分类号： G11C11/419 , G11C7/1051 , G11C8/08 , G11C11/412 , G11C11/413
摘要： A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells in the row operate in a first mode. The method further includes controlling at least one transistor using the at least one write word line signal to connect the plurality of memory cells in the row to a reference voltage when the plurality of memory cells in the row operate in a second mode.
摘要翻译：一种控制一行中的多个存储单元的方法。该方法包括当行中的多个存储单元在第一模式下操作时，使用至少一个写字线信号来控制开关元件，以提高连接到行中的多个存储单元的节点的电压。该方法还包括：当行中的多个存储器单元以第二模式操作时，使用至少一个写入字线信号来控制至少一个晶体管，以将该行中的多个存储单元连接到参考电压。

4. 发明授权

US08362807B2 Offset compensation for sense amplifiers 有权
标题翻译：读出放大器的偏移补偿
公开(公告)号：US08362807B2
公开(公告)日：2013-01-29
申请号：US12903652
申请日：2010-10-13
申请人： Bharath Upputuri , Shreekanth Sampigethaya
发明人： Bharath Upputuri , Shreekanth Sampigethaya
IPC分类号： G11C7/00 , H03F3/45
CPC分类号： H03F1/301 , G01R27/02 , G11C7/06 , G11C7/065 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/12 , H03F3/45179 , H03F2200/471 , H03F2203/45588
摘要： A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages.
摘要翻译：描述了一种具有补偿电路的读出放大器。补偿电路包括至少一对补偿晶体管。当需要补偿时，至少一对补偿晶体管的大部分组合中的一个或组合被提供有补偿电压的一个或组合。

5. 发明申请

US20120243347A1 MEMORY CELLS HAVING A ROW-BASED READ AND/OR WRITE SUPPORT CIRCUITRY 有权
标题翻译：具有基于读取和/或写入支持电路的存储单元
公开(公告)号：US20120243347A1
公开(公告)日：2012-09-27
申请号：US13489055
申请日：2012-06-05
申请人： Shreekanth SAMPIGETHAYA , Bharath UPPUTURI
发明人： Shreekanth SAMPIGETHAYA , Bharath UPPUTURI
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/1051 , G11C8/08 , G11C11/412 , G11C11/413
摘要： A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells in the row operate in a first mode. The method further includes controlling at least one transistor using the at least one write word line signal to connect the plurality of memory cells in the row to a reference voltage when the plurality of memory cells in the row operate in a second mode.
摘要翻译：一种控制一行中的多个存储单元的方法。该方法包括当行中的多个存储单元在第一模式下操作时，使用至少一个写字线信号来控制开关元件，以提高连接到行中的多个存储单元的节点的电压。该方法还包括：当行中的多个存储器单元以第二模式操作时，使用至少一个写入字线信号来控制至少一个晶体管，以将该行中的多个存储单元连接到参考电压。

6. 发明授权

US08213242B2 Memory cells having a row-based read and/or write support circuitry 有权
标题翻译：存储单元具有基于行的读和/或写支持电路
公开(公告)号：US08213242B2
公开(公告)日：2012-07-03
申请号：US12888860
申请日：2010-09-23
申请人： Shreekanth Sampigethaya , Bharath Upputuri
发明人： Shreekanth Sampigethaya , Bharath Upputuri
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/1051 , G11C8/08 , G11C11/412 , G11C11/413
摘要： A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.
摘要翻译：一个电路包括一行中的多个存储器单元，至少一个写入字线和耦合到该至少一个写入字线和该行中多个存储单元的写入支持电路。写支持电路包括第一电流路径和至少一个第二电流路径。所述至少一个第二电流路径的电流路径对应于所述至少一个写入字线的相应写入字线。所述至少一个写入字线的写入字线被配置为当所述行中的所述多个存储器单元以第一模式操作时选择所述第一电流路径，并且选择所述至少一个第二电流路径的第二电流路径当行中的多个存储单元在第二模式下操作时。

7. 发明授权

US08185851B2 Memory building blocks and memory design using automatic design tools 有权
标题翻译：使用自动设计工具的内存构建块和内存设计
公开(公告)号：US08185851B2
公开(公告)日：2012-05-22
申请号：US12825960
申请日：2010-06-29
申请人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
发明人： Subramani Kengeri , Chung-Cheng Chou , Bharath Upputuri , Hank Cheng , Ming-Zhang Kuo , Pey-Huey Chen
IPC分类号： G06F9/45
CPC分类号： G06F17/5045
摘要： The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.
摘要翻译：存储器构建块可以与ASIC自动设计工具结合使用，以使用已知ASIC设计流程来生成存储器宏（例如，存储器阵列），其包括例如寄存器传输级（RTL），合成，自动位置和路由（APR）和时序分析。

8. 发明申请

US20120075939A1 MEMORY CELLS HAVING A ROW-BASED READ AND/OR WRITE SUPPORT CIRCUITRY 有权
标题翻译：具有基于读取和/或写入支持电路的存储单元
公开(公告)号：US20120075939A1
公开(公告)日：2012-03-29
申请号：US12888860
申请日：2010-09-23
申请人： Shreekanth SAMPIGETHAYA , Bharath UPPUTURI
发明人： Shreekanth SAMPIGETHAYA , Bharath UPPUTURI
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/1051 , G11C8/08 , G11C11/412 , G11C11/413
摘要： A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.
摘要翻译：一个电路包括一行中的多个存储器单元，至少一个写入字线和耦合到该至少一个写入字线和该行中多个存储器单元的写入支持电路。写支持电路包括第一电流路径和至少一个第二电流路径。所述至少一个第二电流路径的电流路径对应于所述至少一个写入字线的相应写入字线。所述至少一个写入字线的写入字线被配置为当所述行中的所述多个存储器单元以第一模式操作时选择所述第一电流路径，并且选择所述至少一个第二电流路径的第二电流路径当行中的多个存储单元在第二模式下操作时。

9. 发明申请

US20110198923A1 POWER MANAGEMENT MECHANISM 有权
标题翻译：电力管理机制
公开(公告)号：US20110198923A1
公开(公告)日：2011-08-18
申请号：US12706849
申请日：2010-02-17
申请人： Hank CHENG , Bharath Upputuri
发明人： Hank CHENG , Bharath Upputuri
IPC分类号： H02J1/00
CPC分类号： G06F1/26 , G06F1/28 , G11C7/12 , H02M3/335 , Y10T307/406
摘要： An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.
摘要翻译：集成电路包括全局电源节点。第一电源域具有第一电源管理电路，其包括本地电源节点。第一功率控制电路能够接收输入信号。第二功率控制电路具有比第一功率控制电路更高的电流容量。第一功率控制电路和第二功率控制电路耦合到本地电源节点和全局电源节点。输入信号被配置为在第一功率控制电路中启动功率序列，例如上电过程或断电过程。由第一功率控制电路产生的第一控制信号被配置为启动第二功率控制电路中的功率序列。

10. 发明申请

US20120274135A1 POWER MANAGEMENT MECHANISM 有权
标题翻译：电力管理机制
公开(公告)号：US20120274135A1
公开(公告)日：2012-11-01
申请号：US13536819
申请日：2012-06-28
申请人： Hank CHENG , Bharath UPPUTURI
发明人： Hank CHENG , Bharath UPPUTURI
IPC分类号： H02J1/00
CPC分类号： G06F1/26 , G06F1/28 , G11C7/12 , H02M3/335 , Y10T307/406
摘要： An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.
摘要翻译：集成电路包括全局电源节点。第一电源域具有第一电源管理电路，其包括本地电源节点。第一功率控制电路能够接收输入信号。第二功率控制电路具有比第一功率控制电路更高的电流容量。第一功率控制电路和第二功率控制电路耦合到本地电源节点和全局电源节点。输入信号被配置为在第一功率控制电路中启动功率序列，例如上电过程或断电过程。由第一功率控制电路产生的第一控制信号被配置为启动第二功率控制电路中的功率序列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式