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1. 发明授权

US06281063B1 Method for manufacturing trench isolation 失效
标题翻译：沟槽隔离方法
公开(公告)号：US06281063B1
公开(公告)日：2001-08-28
申请号：US09690519
申请日：2000-10-17
申请人： Yi-Min Jen , Kuan-Te Pai
发明人： Yi-Min Jen , Kuan-Te Pai
IPC分类号： H01L218238
CPC分类号： H01L21/76202 , H01L21/76235
摘要： A method for manufacturing a trench isolation in a semiconductor device is disclosed, wherein a silicon nitride layer used as an anti-diffusion layer mask that defines an isolation region on a silicon substrate and a thermal oxidation process that is performed on active regions are previously used. A silicon substrate having a first pad oxide layer and a first silicon nitride layer formed thereon is first provided. Then the first pad oxide layer and the first silicon nitride layer are patterned to form an anti-diffusion layer mask and to expose an active region of the silicon substrate. Next the silicon substrate is oxidized to form a first silicon dioxide layer, wherein lateral oxidation on the active region of the silicon substrate underneath the first pad oxide layer and the first silicon nitride layer provides an edge of the first silicon dioxide layer in the shape of a bird's beak. Moreover, the first silicon nitride layer, the first pad oxide layer and the first silicon dioxide layer are removed to expose the silicon substrate. Furthermore, a second pad oxide layer is formed on the substrate and a second silicon nitride layer is deposited thereon. Finally, an isolation trench of the invention can be formed by using a conventional method.
摘要翻译：公开了一种在半导体器件中制造沟槽隔离的方法，其中预先使用用作限定硅衬底上的隔离区域的抗扩散层掩模的氮化硅层和在有源区上执行的热氧化工艺。首先提供具有形成在其上的第一衬垫氧化物层和第一氮化硅层的硅衬底。然后对第一衬垫氧化物层和第一氮化硅层进行构图以形成抗扩散层掩模并暴露硅衬底的有源区。接下来，硅衬底被氧化以形成第一二氧化硅层，其中在第一衬垫氧化物层和第一氮化硅层下面的硅衬底的有源区上的侧向氧化提供第一二氧化硅层的边缘，一只鸟的喙。此外，去除第一氮化硅层，第一衬垫氧化物层和第一二氧化硅层以暴露硅衬底。此外，在衬底上形成第二衬垫氧化物层，并在其上沉积第二氮化硅层。最后，可以通过使用常规方法形成本发明的隔离沟槽。

2. 发明授权

US06440804B1 Static random access memory manufacturing method 失效
标题翻译：静态随机存取存储器制造方法
公开(公告)号：US06440804B1
公开(公告)日：2002-08-27
申请号：US09945052
申请日：2001-08-31
申请人： Yi-Min Jen
发明人： Yi-Min Jen
IPC分类号： H01L218244
CPC分类号： H01L27/11
摘要： A static random access memory manufacturing method. A substrate having a gate oxide layer and a first conducting layer is defined to form a buried contact window opening. A second conducting layer is formed upon the substrate with a recess structure at the region of the buried contact opening. A buried contact window is formed in the substrate under the buried contact window opening. A protective layer is formed upon the substrate and fills the recess. A portion of the protective layer is removed, and a patterned photoresist layer is formed upon the substrate. Using the photoresist as a mask, the first and second conducting layer are etched to form a gate electrode and an interconnect. The patterned photoresist layer is removed. The protective layer can be removed or retained. An implantation procedure is performed, thereby forming a source/drain, thereby connecting the source/drain and the contact window.
摘要翻译：一种静态随机存取存储器制造方法。限定具有栅极氧化物层和第一导电层的衬底以形成掩埋接触窗口。第二导电层在掩埋接触开口的区域处形成在具有凹陷结构的基底上。在掩埋接触窗口下面的衬底中形成掩埋接触窗口。在基板上形成保护层并填充凹部。去除保护层的一部分，并且在衬底上形成图案化的光致抗蚀剂层。使用光致抗蚀剂作为掩模，蚀刻第一和第二导电层以形成栅电极和互连。去除图案化的光致抗蚀剂层。保护层可以被去除或保留。进行植入程序，从而形成源极/漏极，由此连接源极/漏极和接触窗口。

3. 发明授权

US06303467B1 Method for manufacturing trench isolation 失效
标题翻译：沟槽隔离方法
公开(公告)号：US06303467B1
公开(公告)日：2001-10-16
申请号：US09628675
申请日：2000-07-28
申请人： Yi-Min Jen , Tse-Yi Lu , Ya-Ling Hung , Li-Wu Tsao
发明人： Yi-Min Jen , Tse-Yi Lu , Ya-Ling Hung , Li-Wu Tsao
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for manufacturing trench isolation, comprising firstly, defining a trench isolation over the substrate by photolithography and etching technique. Beside, by way of a spacer fabricating process to form a spacer around each of the two sides of the trench isolation. Therefore, a sharp corner in the crossing region between the trench isolation and an active area adjacent thereto in the substrate is smoothed, and the process window for a sequential gate polysilicon etching is improved, as well as the opportunity to leave polysilicon residue in the corner is eliminated. The short circuit between polysilicon gates is also avoided.
摘要翻译：一种用于制造沟槽隔离的方法，首先，通过光刻和蚀刻技术在衬底上限定沟槽隔离。此外，通过间隔件制造工艺，在沟槽隔离的两侧的每一侧上形成间隔件。因此，在沟槽隔离和与衬底之间相邻的有源区域之间的交叉区域中的尖角被平滑化，并且用于顺序栅极多晶硅蚀刻的处理窗口以及在多个晶圆中留下多晶硅残留物的机会被淘汰。也避免了多晶硅栅之间的短路。

4. 发明授权

US06495417B1 Method for increasing tolerance of contact extension alignment in COB DRAM 有权
标题翻译：增加COB DRAM中接触扩展对准容限的方法
公开(公告)号：US06495417B1
公开(公告)日：2002-12-17
申请号：US09669940
申请日：2000-09-26
申请人： Yu-Ju Yang , Yi-Min Jen , Kuo-Yuh Yang , Yu-Hong Huang
发明人： Yu-Ju Yang , Yi-Min Jen , Kuo-Yuh Yang , Yu-Hong Huang
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L21/76897 , H01L28/60
摘要： A method for increasing tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory is disclosed. Firstly, a substrate having a gate, a bit line and a source/drain region is provided and a insulating layer is formed on the substrate. Then, a dielectric layer is deposited on the insulating layer. Moreover, a contact hole is formed by defining and etching the dielectric layer and the insulating layer to expose a portion of the source/drain region. Furthermore, a conductive layer is deposited on the dielectric layer and the contact hole, wherein the etching selectivity ratio of the conductive layer is near the etching selectivity ratio of the dielectric layer. Finally, an electrode of the capacitor is formed by defining and etching the conductive layer, whereby the dielectric layer protects the portion of the electrode that is beneath the dielectric layer from being etched when misalignment occurs.
摘要翻译：公开了一种用于在动态随机存取存储器的位线上增加电容器中接触延伸对准的容限的方法。首先，提供具有栅极，位线和源极/漏极区域的衬底，并且在衬底上形成绝缘层。然后，在绝缘层上沉积电介质层。此外，通过限定和蚀刻介电层和绝缘层来形成接触孔以暴露源/漏区的一部分。此外，在电介质层和接触孔上沉积导电层，其中导电层的蚀刻选择比接近电介质层的蚀刻选择比。最后，通过限定和蚀刻导电层来形成电容器的电极，由此当发生不对准时，电介质层保护电介质层下方的电极部分不被蚀刻。

5. 发明授权

US6103608A Method of forming a contact window 失效
标题翻译：形成接触窗的方法
公开(公告)号：US6103608A
公开(公告)日：2000-08-15
申请号：US62661
申请日：1998-04-20
申请人： Yi-Min Jen , Chung-Hsien Wu
发明人： Yi-Min Jen , Chung-Hsien Wu
IPC分类号： H01L21/60 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/76897
摘要： The present invention discloses a method of forming a contact window on a substrate. The method in the present invention includes a step of forming a gate structure on said substrate having a gate oxide, a gate electrode on the gate oxide, and a gate electrode protection layer on the gate electrode, a step of forming a protection layer conforming with the substrate and the gate structure, and a step of forming a first insulation layer over the protection layer. The method further includes removing a portion of the first insulation layer and a portion of the protection layer for forming side wall spacers at side walls of the gate structure, performing a ion implantation to the substrate using the gate structure and the side wall spacers as a mask, and then forming a second insulation layer on the substrate, the side wall spacers, and the gate structure. The method further includes patterning a photoresist layer on the second insulation layer to expose a portion of second insulation layer for making a connection. Finally, a portion of the second insulation layer is removed for forming a contact window.
摘要翻译：本发明公开了一种在基板上形成接触窗的方法。本发明的方法包括：在具有栅极氧化物的栅极结构上形成栅极结构的步骤，栅极氧化物上的栅电极和栅电极上的栅电极保护层，形成与基板和栅极结构，以及在保护层上形成第一绝缘层的步骤。该方法还包括去除第一绝缘层的一部分和用于在栅极结构的侧壁处形成侧壁间隔物的保护层的一部分，使用栅极结构和侧壁间隔物作为离子注入到基底掩模，然后在衬底，侧壁间隔物和栅极结构上形成第二绝缘层。该方法还包括在第二绝缘层上图案化光致抗蚀剂层，以露出用于进行连接的第二绝缘层的一部分。最后，去除第二绝缘层的一部分以形成接触窗。

6. 发明授权

US06287909B1 Method of fabricating a static random access memory 有权
标题翻译：制造静态随机存取存储器的方法
公开(公告)号：US06287909B1
公开(公告)日：2001-09-11
申请号：US09578227
申请日：2000-05-24
申请人： Yi-Min Jen , Tse-Yi Lu , Yu-Chih Chuang
发明人： Yi-Min Jen , Tse-Yi Lu , Yu-Chih Chuang
IPC分类号： H01L218234
CPC分类号： H01L27/11
摘要： A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact.
摘要翻译：一种在静态随机存取存储器中制造掩埋触点的方法。栅极氧化层，第一导电层和掩模层依次形成在基板上。掩模接触开口形成在栅极氧化物层内，第一导电层和掩蔽层中，该开口露出基板的一部分。在埋入接触开口内形成外延层，该外延层填充埋入的接触开口。在去除掩模层之后，在衬底上方形成第二导电层。在衬底中形成在外延层下面的掩埋接触。图案化栅极氧化物层，第一导电层，外延层和第二导电层，以暴露衬底的一部分和埋入触点的一部分。源极/漏极形成在衬底中，并且源极/漏极的一部分与埋入触点的一部分混合。

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