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1. 发明申请

US20130044046A1 DISPLAY PANEL 有权
标题翻译：显示面板
公开(公告)号：US20130044046A1
公开(公告)日：2013-02-21
申请号：US13471480
申请日：2012-05-15
申请人： Yen-Shih Huang , Chia-Yuan Yeh , Bo-Feng Lee , Ta-Wei Chiu
发明人： Yen-Shih Huang , Chia-Yuan Yeh , Bo-Feng Lee , Ta-Wei Chiu
IPC分类号： G09G3/30
CPC分类号： H01L51/524 , H01L27/3258 , H01L27/3276
摘要： A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.
摘要翻译：显示面板包括基板，TFT器件，图案化电介质层，图案化金属层和桥接线。 TFT器件设置在显示区域中。图案化电介质层包括设置在TFT器件上的ILD层和设置在周边区域中的密封剂级。图案化金属层包括设置在ILD层上的信号线，以及第一连接线和第二连接线。第一连接线设置在面向显示区域的密封剂阶段的内侧，并且第一连接线电连接到信号线。第二连接线设置在与显示区域相对的密封剂台的外侧。桥接线设置在密封剂阶段下方，第一连接线和第二连接线通过桥接线电连接。

2. 发明授权

US09070897B2 Display panel 有权
标题翻译：显示面板
公开(公告)号：US09070897B2
公开(公告)日：2015-06-30
申请号：US13471480
申请日：2012-05-15
申请人： Yen-Shih Huang , Chia-Yuan Yeh , Bo-Feng Lee , Ta-Wei Chiu
发明人： Yen-Shih Huang , Chia-Yuan Yeh , Bo-Feng Lee , Ta-Wei Chiu
IPC分类号： H01L27/12 , H01L51/52 , H01L27/32
CPC分类号： H01L51/524 , H01L27/3258 , H01L27/3276
摘要： A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.
摘要翻译：显示面板包括基板，TFT器件，图案化电介质层，图案化金属层和桥接线。 TFT器件设置在显示区域中。图案化电介质层包括设置在TFT器件上的ILD层和设置在周边区域中的密封剂级。图案化金属层包括设置在ILD层上的信号线，以及第一连接线和第二连接线。第一连接线设置在面向显示区域的密封剂阶段的内侧，并且第一连接线电连接到信号线。第二连接线设置在与显示区域相对的密封剂台的外侧。桥接线设置在密封剂阶段下方，第一连接线和第二连接线通过桥接线电连接。

3. 发明申请

US20120305910A1 HYBRID THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND DISPLAY PANEL HAVING THE SAME 有权
标题翻译：混合薄膜晶体管及其制造方法及其显示面板
公开(公告)号：US20120305910A1
公开(公告)日：2012-12-06
申请号：US13234119
申请日：2011-09-15
申请人： Hsiu-Chun Hsieh , Yi-Wei Chen , Ta-Wei Chiu , Chung-Tao Chen
发明人： Hsiu-Chun Hsieh , Yi-Wei Chen , Ta-Wei Chiu , Chung-Tao Chen
IPC分类号： H01L29/24 , H01L33/16 , H01L29/786 , H01L21/336
CPC分类号： H01L27/1225 , H01L27/1222 , H01L27/1251
摘要： A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.
摘要翻译：混合薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管。第一薄膜晶体管包括第一栅极，第一源极，第一漏极和设置在第一栅极，第一源极和第一漏极之间的第一半导体层，并且第一半导体层包括结晶硅层。第二薄膜晶体管包括第二栅极，第二源极，第二漏极和设置在第二栅极，第二源极和第二漏极之间的第二半导体层，第二半导体层包括金属氧化物半导体层。

4. 发明申请

US20080224142A1 Semiconductor Structure of Liquid Crystal Display and Manufacturing Method Thereof 有权
标题翻译：液晶显示器的半导体结构及其制造方法
公开(公告)号：US20080224142A1
公开(公告)日：2008-09-18
申请号：US12017162
申请日：2008-01-21
申请人： Yi-Sheng Cheng , Ta-Wei Chiu
发明人： Yi-Sheng Cheng , Ta-Wei Chiu
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L27/1288 , H01L27/1255
摘要： A semiconductor structure of a liquid crystal display and the manufacturing method thereof are described. The manufacturing method includes the following steps. A patterned polysilicon layer and a first dielectric layer are formed on a substrate. A first patterned metal layer is formed to construct a gate electrode and a capacitor electrode. An ion implantation is conducted on the polysilicon layer to form drain and source electrodes. A second dielectric layer and a second patterned metal layer are formed thereon. Sequentially, a third dielectric layer is formed thereon. A plurality of via openings are formed by a patterned photoresist layer, and a third metal layer is formed thereon and filled into the via openings. The patterned photoresist layer and the redundant third metal layer are stripped from the substrate to form via plugs in the via openings. A patterned transparent conductive layer is formed thereon to connect the via plugs.
摘要翻译：对液晶显示器的半导体结构及其制造方法进行说明。该制造方法包括以下步骤。在基板上形成图形化的多晶硅层和第一介质层。形成第一图案化金属层以构成栅电极和电容器电极。在多晶硅层上进行离子注入以形成漏极和源极。在其上形成第二介电层和第二图案化金属层。接着，在其上形成第三电介质层。通过图案化的光致抗蚀剂层形成多个通路孔，并且在其上形成第三金属层并填充到通孔中。图案化的光致抗蚀剂层和冗余的第三金属层从基板剥离以在通孔开口中形成通孔塞。在其上形成图案化的透明导电层以连接通孔塞。

5. 发明授权

US08093596B2 Pixel structure 有权
标题翻译：像素结构
公开(公告)号：US08093596B2
公开(公告)日：2012-01-10
申请号：US12815394
申请日：2010-06-14
申请人： Ta-Wei Chiu , Yi-Sheng Cheng , Shih-Yi Yen
发明人： Ta-Wei Chiu , Yi-Sheng Cheng , Shih-Yi Yen
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L28/60 , G02F2001/136231 , H01L27/1255 , H01L27/1288
摘要： A pixel structure includes a patterned semiconductor layer disposed on a transistor region of the substrate, a first capacitor electrode disposed on a capacitor region of the substrate, a gate dielectric layer disposed on the first capacitor electrode, a gate disposed on a channel region of the patterned semiconductor layer, a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region, a first dielectric layer disposed on the gate and the aluminum capacitor electrode, at least one first wire disposed in the first dielectric layer for electrically connecting source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode, a second dielectric layer disposed on the first wire, and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.
摘要翻译：像素结构包括设置在基板的晶体管区域上的图案化半导体层，设置在基板的电容器区域上的第一电容器电极，设置在第一电容器电极上的栅极介电层，设置在第一电容器电极的沟道区上的栅极图案化半导体层，第二电容器电极，电介质层和依次设置在电容器区的栅极电介质层上的铝电容器电极，设置在栅极和铝电容器电极上的第一电介质层，至少一个第一布线在用于电连接图案化半导体层的源极/漏极区域和铝电容器电极的第一电介质层中，设置在第一线路上的第二电介质层和设置在第二电介质层上并连接到第一电介质层的第一透明导电层线。

6. 发明授权

US07763479B2 Pixel structure and method of fabricating the same 有权
标题翻译：像素结构及其制造方法
公开(公告)号：US07763479B2
公开(公告)日：2010-07-27
申请号：US12017338
申请日：2008-01-22
申请人： Ta-Wei Chiu , Yi-Sheng Cheng , Shih-Yi Yen
发明人： Ta-Wei Chiu , Yi-Sheng Cheng , Shih-Yi Yen
IPC分类号： H01L21/00 , H01L29/06
CPC分类号： H01L28/60 , G02F2001/136231 , H01L27/1255 , H01L27/1288
摘要： A method for fabricating pixel structures is disclosed. Specifically, the present invention deposits a conductive layer, a gate dielectric layer, and an aluminum layer on a gate dielectric layer, and performs an isotropic etching process to evenly etch a portion of the aluminum layer in the horizontal and vertical direction. By following this process, the number of photomasks used before the formation of the source/drain region can be reduced, and the conductive layer and the aluminum layer disposed on the capacitor electrode in the capacitor region can be used to increase the capacitance of the capacitor.
摘要翻译：公开了一种用于制造像素结构的方法。具体地说，本发明在栅介质层上沉积导电层，栅极电介质层和铝层，并执行各向同性蚀刻工艺以在水平和垂直方向均匀地蚀刻铝层的一部分。通过跟随该处理，可以减少在形成源极/漏极区域之前使用的光掩模的数量，并且可以使用设置在电容器区域中的电容器电极上的导电层和铝层来增加电容器的电容。

7. 发明授权

US08829511B2 Hybrid thin film transistor, manufacturing method thereof and display panel having the same 有权
标题翻译：混合薄膜晶体管，其制造方法和具有该混合薄膜晶体管的显示面板
公开(公告)号：US08829511B2
公开(公告)日：2014-09-09
申请号：US13234119
申请日：2011-09-15
申请人： Hsiu-Chun Hsieh , Yi-Wei Chen , Ta-Wei Chiu , Chung-Tao Chen
发明人： Hsiu-Chun Hsieh , Yi-Wei Chen , Ta-Wei Chiu , Chung-Tao Chen
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L27/1225 , H01L27/1222 , H01L27/1251
摘要： A hybrid thin film transistor includes a first thin film transistor and a second thin film transistor. The first thin film transistor includes a first gate, a first source, a first drain and a first semiconductor layer disposed between the first gate, the first source and the first drain, and the first semiconductor layer includes a crystallized silicon layer. The second thin film transistor includes a second gate, a second source, a second drain and a second semiconductor layer disposed between the second gate, the second source and the second drain, and the second semiconductor layer includes a metal oxide semiconductor layer.
摘要翻译：混合薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管。第一薄膜晶体管包括第一栅极，第一源极，第一漏极和设置在第一栅极，第一源极和第一漏极之间的第一半导体层，并且第一半导体层包括结晶硅层。第二薄膜晶体管包括第二栅极，第二源极，第二漏极和设置在第二栅极，第二源极和第二漏极之间的第二半导体层，第二半导体层包括金属氧化物半导体层。

8. 发明申请

US20120049197A1 PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：像素结构及其制造方法
公开(公告)号：US20120049197A1
公开(公告)日：2012-03-01
申请号：US13004034
申请日：2011-01-11
申请人： Hsiu-Chun Hsieh , Yi-Wei Chen , Ta-Wei Chiu , Chung-Tao Chen
发明人： Hsiu-Chun Hsieh , Yi-Wei Chen , Ta-Wei Chiu , Chung-Tao Chen
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1237
摘要： A pixel structure is provided. A first insulating pattern is on the first polysilicon pattern. A second insulating pattern is on the second polysilicon pattern and separated from the first insulating pattern. An insulating layer covers the first and the second insulating patterns. A first gate and a second gate are on the insulating layer. A first covering layer covers the first and the second gates. A first source metal layer and a first drain metal layer are on the first covering layer and electrically connected to a first source region and a first drain region. A second source metal layer and a second drain metal layer are on the first covering layer and electrically connected to a second source region and a second drain region. A pixel electrode is electrically connected to the first drain metal layer.
摘要翻译：提供像素结构。第一绝缘图案在第一多晶硅图案上。第二绝缘图案在第二多晶硅图案上并且与第一绝缘图案分离。绝缘层覆盖第一和第二绝缘图案。第一栅极和第二栅极位于绝缘层上。第一覆盖层覆盖第一和第二栅极。第一源极金属层和第一漏极金属层在第一覆盖层上并且电连接到第一源极区域和第一漏极区域。第二源极金属层和第二漏极金属层在第一覆盖层上并且电连接到第二源极区域和第二漏极区域。像素电极电连接到第一漏极金属层。

9. 发明授权

US07601552B2 Semiconductor structure of liquid crystal display and manufacturing method thereof 有权
标题翻译：液晶显示器的半导体结构及其制造方法
公开(公告)号：US07601552B2
公开(公告)日：2009-10-13
申请号：US12017162
申请日：2008-01-21
申请人： Yi-Sheng Cheng , Ta-Wei Chiu
发明人： Yi-Sheng Cheng , Ta-Wei Chiu
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , H01L27/1255
摘要： A semiconductor structure of a liquid crystal display and the manufacturing method thereof are described. The manufacturing method includes the following steps. A patterned polysilicon layer and a first dielectric layer are formed on a substrate. A first patterned metal layer is formed to construct a gate electrode and a capacitor electrode. An ion implantation is conducted on the polysilicon layer to form drain and source electrodes. A second dielectric layer and a second patterned metal layer are formed thereon. Sequentially, a third dielectric layer is formed thereon. A plurality of via openings are formed by a patterned photoresist layer, and a third metal layer is formed thereon and filled into the via openings. The patterned photoresist layer and the redundant third metal layer are stripped from the substrate to form via plugs in the via openings. A patterned transparent conductive layer is formed thereon to connect the via plugs.
摘要翻译：对液晶显示器的半导体结构及其制造方法进行说明。该制造方法包括以下步骤。在基板上形成图形化的多晶硅层和第一介质层。形成第一图案化金属层以构成栅电极和电容器电极。在多晶硅层上进行离子注入以形成漏极和源极。在其上形成第二介电层和第二图案化金属层。接着，在其上形成第三电介质层。通过图案化的光致抗蚀剂层形成多个通路孔，并且在其上形成第三金属层并填充到通孔中。图案化的光致抗蚀剂层和冗余的第三金属层从基板剥离以在通孔开口中形成通孔塞。在其上形成图案化的透明导电层以连接通孔塞。

10. 发明申请

US20120025320A1 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATING METHOD THEREOF 有权
标题翻译：补充金属氧化物半导体晶体管及其制造方法
公开(公告)号：US20120025320A1
公开(公告)日：2012-02-02
申请号：US12943006
申请日：2010-11-10
申请人： Chung-Tao Chen , Ta-Wei Chiu , Yu-Pu Lin , Yi-Wei Chen
发明人： Chung-Tao Chen , Ta-Wei Chiu , Yu-Pu Lin , Yi-Wei Chen
IPC分类号： H01L27/092 , H01L51/40 , H01L21/8238
CPC分类号： H01L27/286 , H01L21/441 , H01L21/467 , H01L27/1225 , H01L27/1251 , H01L27/281 , H01L29/6675 , H01L29/66969 , H01L29/7869 , H01L51/0018 , H01L51/0021 , H01L51/0053 , H01L51/0068 , H01L51/0072 , H01L51/0545
摘要： A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.
摘要翻译： CMOS晶体管的制造方法包括以下步骤。在基板上形成第一栅极和第二栅极。栅极绝缘体形成在衬底上以覆盖第一和第二栅极。第一源极，第一漏极，第二源极和第二漏极形成在栅极绝缘体上。第一个源极和第一个漏极位于第一个栅极之上。第二源极和第二漏极位于第二栅极之上。在栅极绝缘体上形成第一沟道层和掩模层。掩模层位于第一通道层上。第一沟道层位于第一栅极之上并且与第一源极和第一漏极接触。在栅极绝缘体上形成第二沟道层。第二通道层位于第二栅极之上并与第二源极和第二漏极接触。

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