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    • 2. 发明申请
    • DISPLAY PANEL
    • 显示面板
    • US20130044046A1
    • 2013-02-21
    • US13471480
    • 2012-05-15
    • Yen-Shih HuangChia-Yuan YehBo-Feng LeeTa-Wei Chiu
    • Yen-Shih HuangChia-Yuan YehBo-Feng LeeTa-Wei Chiu
    • G09G3/30
    • H01L51/524H01L27/3258H01L27/3276
    • A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.
    • 显示面板包括基板,TFT器件,图案化电介质层,图案化金属层和桥接线。 TFT器件设置在显示区域中。 图案化电介质层包括设置在TFT器件上的ILD层和设置在周边区域中的密封剂级。 图案化金属层包括设置在ILD层上的信号线,以及第一连接线和第二连接线。 第一连接线设置在面向显示区域的密封剂阶段的内侧,并且第一连接线电连接到信号线。 第二连接线设置在与显示区域相对的密封剂台的外侧。 桥接线设置在密封剂阶段下方,第一连接线和第二连接线通过桥接线电连接。
    • 7. 发明授权
    • Pixel array layout
    • 像素阵列布局
    • US08164544B2
    • 2012-04-24
    • US12506257
    • 2009-07-21
    • Chen-Wei LinYen-Shih Huang
    • Chen-Wei LinYen-Shih Huang
    • G09G3/20
    • G09G3/3233G09G2300/0842G09G2310/0251G09G2310/0254G09G2310/0262G09G2320/043H01L27/326H01L27/3276
    • A pixel array layout includes a substrate, a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, a plurality of pixel units disposed on the substrate, and a pre-discharge conductive layer. Each of the pixel units is electrically connected to at least one of the scan lines and one of the data lines correspondingly, and each of the pixel units has a driving circuit and a pixel electrode electrically connected to the driving circuit. The pre-discharge conductive layer is electrically connected to the driving circuit and extends to an area between two adjacent pixel electrodes from an edge of the substrate, and the pre-discharge conductive layer and the pixel electrodes do not overlap.
    • 像素阵列布局包括衬底,设置在衬底上的多条扫描线,设置在衬底上的多条数据线,设置在衬底上的多个像素单元和预放电导电层。 每个像素单元相应地电连接到扫描线和数据线中的至少一个,并且每个像素单元具有电连接到驱动电路的驱动电路和像素电极。 预放电导电层与驱动电路电连接,从基板的边缘延伸到两个相邻像素电极之间的区域,并且预放电导电层和像素电极不重叠。