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1. 发明授权

US08669816B2 Integrated circuit device, electronic device and method therefor 有权
标题翻译：集成电路器件，电子器件及其方法
公开(公告)号：US08669816B2
公开(公告)日：2014-03-11
申请号：US13273231
申请日：2011-10-14
申请人： Yen-Horng Chen , Augusto Marques , Caiyi Wang
发明人： Yen-Horng Chen , Augusto Marques , Caiyi Wang
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L1/00 , H03L1/02 , H03L2207/06 , H03L2207/50
摘要： An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.
摘要翻译：集成电路装置包括至少一个包括第一控制端口和至少一个另外的控制端口的可控振荡器，至少一个频率控制模块，其包括布置成提供频率控制信号的输出。所述至少一个可控振荡器还包括至少一个补偿模块，该补偿模块包括布置成提供至少一个补偿信号的输出。所述至少一个补偿模块包括积分器部件，其被布置为在其输入处接收表示所述频率控制信号的指示与参考信号之间的差异的信号，并输出积分差分信号。至少一个补偿模块被布置成至少部分地基于由积分器组件输出的积分差分信号来产生至少一个补偿信号。

2. 发明申请

US20120074993A1 INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD THEREFOR 有权
标题翻译：集成电路设备，电子设备及其方法
公开(公告)号：US20120074993A1
公开(公告)日：2012-03-29
申请号：US13273231
申请日：2011-10-14
申请人： Yen-Horng Chen , Augusto Marques , Caiyi Wang
发明人： Yen-Horng Chen , Augusto Marques , Caiyi Wang
IPC分类号： H03L7/08
CPC分类号： H03L7/099 , H03L1/00 , H03L1/02 , H03L2207/06 , H03L2207/50
摘要： An integrated circuit device includes at least one controllable oscillator including a first control port and at least one further control port, at least one frequency control module including an output arranged to provide a frequency control signal. The at least one controllable oscillator further includes at least one compensation module including an output arranged to provide at least one compensation signal. The at least one compensation module includes an integrator component arranged to receive at an input thereof a signal that is representative of a difference between the indication of the frequency control signal and a reference signal, and to output an integrated difference signal. The at least one compensation module is arranged to generate the at least one compensation signal based at least partly on the integrated difference signal output by the integrator component.
摘要翻译：集成电路装置包括至少一个包括第一控制端口和至少一个另外的控制端口的可控振荡器，至少一个频率控制模块，其包括布置成提供频率控制信号的输出。所述至少一个可控振荡器还包括至少一个补偿模块，该补偿模块包括布置成提供至少一个补偿信号的输出。所述至少一个补偿模块包括积分器部件，其被布置为在其输入处接收表示所述频率控制信号的指示与参考信号之间的差异的信号，并输出积分差分信号。至少一个补偿模块被布置成至少部分地基于由积分器组件输出的积分差分信号来产生至少一个补偿信号。

3. 发明授权

US08531322B2 Time-to-digital converter 有权
标题翻译：时间到数字转换器
公开(公告)号：US08531322B2
公开(公告)日：2013-09-10
申请号：US13450263
申请日：2012-04-18
申请人： Changhua Cao , Xiaochuan Guo , Yen-Horng Chen , Caiyi Wang
发明人： Changhua Cao , Xiaochuan Guo , Yen-Horng Chen , Caiyi Wang
IPC分类号： H03M1/48
CPC分类号： G04F10/005
摘要： Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.
摘要翻译：提供了一种时间 - 数字转换器的实施例，包括延迟级矩阵和测量电路。延迟级矩阵包括与其耦合的第一和第二延迟线，并且被布置成在第一和第二延迟线中从起始延迟级传播转换信号，其中第一和第二延迟线中的每一个包括相同的数字的延迟级串联耦合，第一和第二延迟线之一中的每个延迟级耦合到另一个延迟线中的对应的延迟级并且可操作以产生延迟信号。测量电路被设置为通过使用测量信号对延迟信号进行采样来确定沿延迟级传播的转换信号的时间，以生成并保持时间的数字表示。

4. 发明申请

US20070054629A1 PARTITIONING OF RADIO-FREQUENCY APPARATUS 有权
标题翻译：无线电频率设备的分配
公开(公告)号：US20070054629A1
公开(公告)日：2007-03-08
申请号：US10730404
申请日：2003-12-08
申请人： James Maligeorgos , Augusto Marques , Lysander Lim , G. Tuttle , Aslamali Rafi , Tod Paulus , Gregory Uehara , Jeffrey Scott , Richard Behrens , Donald Kerth , G. Vishakhadatta , Vishnu Srinivasan , Caiyi Wang
发明人： James Maligeorgos , Augusto Marques , Lysander Lim , G. Tuttle , Aslamali Rafi , Tod Paulus , Gregory Uehara , Jeffrey Scott , Richard Behrens , Donald Kerth , G. Vishakhadatta , Vishnu Srinivasan , Caiyi Wang
IPC分类号： H04B1/38
CPC分类号： H04B1/30 , H03J2200/10 , H04L27/0002
摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.
摘要翻译：包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

5. 发明申请

US20070200539A1 System with linear and switching regulator circuits 有权
标题翻译：具有线性和开关稳压器电路的系统
公开(公告)号：US20070200539A1
公开(公告)日：2007-08-30
申请号：US11362982
申请日：2006-02-27
申请人： Ramkishore Ganti , Caiyi Wang , Augusto Marques
发明人： Ramkishore Ganti , Caiyi Wang , Augusto Marques
IPC分类号： G05F1/00
CPC分类号： G05F1/56 , H02M3/155 , H02M2001/0045
摘要： An apparatus comprises a circuit having a power supply node and a linear regulator configured to provide a regulated voltage at the power supply node of the circuit. The apparatus further comprises a switching regulator configured to provide input power to the linear regulator from a power source such as a battery. In some implementations, the circuit is a transceiver circuit.
摘要翻译：一种装置包括具有电源节点的电路和被配置为在电路的电源节点处提供调节电压的线性调节器。该装置还包括开关调节器，其被配置为从诸如电池的电源向线性调节器提供输入功率。在一些实现中，电路是收发器电路。

6. 发明授权

US09095041B2 Method and apparatus for reducing interference 有权
公开(公告)号：US09095041B2
公开(公告)日：2015-07-28
申请号：US11930804
申请日：2007-10-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03K5/00 , H05K9/00 , H03L7/18 , H05K1/02 , H05K3/10
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

7. 发明授权

US08154336B2 Method and apparatus for reducing interference 有权
标题翻译：减少干扰的方法和装置
公开(公告)号：US08154336B2
公开(公告)日：2012-04-10
申请号：US11930596
申请日：2007-10-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03K5/00
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
摘要翻译：提供一种减少电路干扰的方法和装置。提供管理策略，以减少参考杂散和电路干扰。管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。这些技术可以单独使用，或者优选地彼此组合使用。

8. 发明申请

US20100102876A1 METHOD AND APPARATUS FOR REDUCING INTERFERENCE 审中-公开
公开(公告)号：US20100102876A1
公开(公告)日：2010-04-29
申请号：US12650545
申请日：2009-12-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03B1/04
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

9. 发明授权

US07522193B2 Histogram-based automatic gain control method and system for video applications 有权
标题翻译：基于直方图的自动增益控制方法和视频应用系统
公开(公告)号：US07522193B2
公开(公告)日：2009-04-21
申请号：US10862488
申请日：2004-06-07
申请人： Nadi R. Itani , Caiyi Wang , David R. Welland
发明人： Nadi R. Itani , Caiyi Wang , David R. Welland
IPC分类号： H04N5/235 , H04N5/228 , H04N5/217
CPC分类号： H04N5/2352
摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC）耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

10. 发明授权

US07289145B2 Correlated double sampling variable gain amplifier circuit for use in a digital camera 有权
标题翻译：用于数码相机的相关双倍可变增益放大器电路
公开(公告)号：US07289145B2
公开(公告)日：2007-10-30
申请号：US11415000
申请日：2006-05-01
申请人： Sandra Marie Johnson , Shih-Chung Chao , Nadi Rafik Itani , Caiyi Wang , Brannon Craig Harris , Ash Prabala , Douglas R. Holberg , Alan Hansford , Syed Khalid Azim , David R. Welland
发明人： Sandra Marie Johnson , Shih-Chung Chao , Nadi Rafik Itani , Caiyi Wang , Brannon Craig Harris , Ash Prabala , Douglas R. Holberg , Alan Hansford , Syed Khalid Azim , David R. Welland
IPC分类号： H04N5/235
CPC分类号： H04N5/3575 , H04N5/335 , H04N5/361
摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC）耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。

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