专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06442061B1 Single channel four transistor SRAM 有权
标题翻译：单通道四晶体管SRAM
公开(公告)号：US06442061B1
公开(公告)日：2002-08-27
申请号：US09783653
申请日：2001-02-14
申请人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
发明人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/11
摘要： A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
摘要翻译：根据本发明的形成存储单元的方法。第一栅极晶体管由第一晶体管形成。第一栅极晶体管具有第一厚度的栅极氧化物。第一栅极晶体管的源极电连接到第一位线，并且第一栅极晶体管的漏极电连接到第一状态节点。第一栅极晶体管的栅极电连接到存储器单元使能线。第二栅极晶体管也由第一晶体管形成。第二栅极晶体管还具有第一厚度的栅极氧化物。第二栅极晶体管的源极电连接到第二位线，并且第二栅极晶体管的漏极电连接到第二状态节点。第二通栅晶体管的栅极电连接到存储单元使能线。第一状态节点晶体管也由第一晶体管类型形成。第一状态节点晶体管具有第二厚度的栅极氧化物。第一状态节点晶体管的源极电连接到第一状态节点，并且第一状态节点晶体管的漏极电连接到接地线。第一状态节点的门电连接到第二状态节点。第二状态节点晶体管也由第一晶体管类型形成。第二状态节点晶体管也具有第二厚度的栅极氧化物。第二状态节点晶体管的源极电连接到第二状态节点，并且第二状态节点晶体管的漏极电连接到接地线。第二状态节点的门电连接到第一状态节点。

2. 发明授权

US06902958B2 Method for making MOSFET anti-fuse structure 有权
标题翻译：制造MOSFET反熔丝结构的方法
公开(公告)号：US06902958B2
公开(公告)日：2005-06-07
申请号：US10773263
申请日：2004-02-09
申请人： Akira Ito , Douglas D. Smith , Myron J. Buer
发明人： Akira Ito , Douglas D. Smith , Myron J. Buer
IPC分类号： H01L21/336 , H01L21/8246 , H01L23/525 , H01L27/112 , H01L29/76 , H01L29/78 , H01L21/8247
CPC分类号： H01L29/6659 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/7836 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
摘要翻译：反熔丝器件包括衬底和形成在衬底中的侧向间隔开的源极和漏极区域。在源区和漏区之间形成通道。在通道上形成栅极和栅极氧化物，并且在沟道中形成轻掺杂的源极和漏极延伸区域。轻掺杂的源极和漏极区域分别从源极和漏极区域延伸穿过沟道，占据通道的主要部分。通过向栅极和源极区域和漏极区域中的至少一个施加电力来执行反熔丝的编程，以分解栅极氧化物，从而最小化栅极和沟道之间的电阻。

3. 发明授权

US07940593B2 Method and apparatus for verification of a gate oxide fuse element 有权
标题翻译：用于验证栅极氧化物熔丝元件的方法和装置
公开(公告)号：US07940593B2
公开(公告)日：2011-05-10
申请号：US10757259
申请日：2004-01-14
申请人： Myron J. Buer , Douglas D. Smith
发明人： Myron J. Buer , Douglas D. Smith
IPC分类号： G11C17/18 , G11C17/00 , G11C7/00 , G11C17/16 , G11C17/14
CPC分类号： G11C17/18 , G11C17/16 , G11C29/38
摘要： The present invention relates to a method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.
摘要翻译：本发明涉及用于验证与一次可编程CMOS存储器件一起使用的门控熔丝元件的状态的方法和电路。设置第一预期状态并且感测到第一栅极 - 氧保险丝的状态。将第一栅极-nox熔丝的状态与第一预期状态进行比较，以确定它们是否相等，并且产生第一信号。设定第二预期状态，并且感测到第二栅 - 氧保险丝的状态。将第二栅极-nox熔丝的状态与第二预期状态进行比较，以确定它们是否相等，并且产生第二信号。如果第一和第二信号都处于正确状态，则两个信号都为高电平，则产生有效的输出。

4. 发明授权

US07897967B2 Anti-fuse device 有权
标题翻译：防熔断器
公开(公告)号：US07897967B2
公开(公告)日：2011-03-01
申请号：US11094269
申请日：2005-03-31
申请人： Akira Ito , Douglas D. Smith , Myron J. Buer
发明人： Akira Ito , Douglas D. Smith , Myron J. Buer
IPC分类号： H01L29/04
CPC分类号： H01L29/6659 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/7836 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
摘要翻译：反熔丝器件包括衬底和形成在衬底中的侧向间隔开的源极和漏极区域。在源区和漏区之间形成通道。在通道上形成栅极和栅极氧化物，并且在沟道中形成轻掺杂的源极和漏极延伸区域。轻掺杂的源极和漏极区域分别从源极和漏极区域延伸穿过沟道，占据通道的主要部分。通过向栅极和源极区域和漏极区域中的至少一个施加电力来执行反熔丝的编程，以分解栅极氧化物，从而最小化栅极和沟道之间的电阻。

5. 发明授权

US06704236B2 Method and apparatus for verification of a gate oxide fuse element 失效
标题翻译：用于验证栅极氧化物熔丝元件的方法和装置
公开(公告)号：US06704236B2
公开(公告)日：2004-03-09
申请号：US10038021
申请日：2002-01-03
申请人： Myron J. Buer , Douglas D. Smith
发明人： Myron J. Buer , Douglas D. Smith
IPC分类号： G11C1716
CPC分类号： G11C17/18 , G11C17/16 , G11C29/38
摘要： A method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.
摘要翻译：一种用于验证与一次可编程CMOS存储器件一起使用的门控熔丝元件的状态的方法和电路。设置第一预期状态并且感测到第一栅极 - 氧保险丝的状态。将第一栅极-nox熔丝的状态与第一预期状态进行比较，以确定它们是否相等，并且产生第一信号。设定第二预期状态，并且感测到第二栅 - 氧保险丝的状态。将第二栅极-nox熔丝的状态与第二预期状态进行比较，以确定它们是否相等，并且产生第二信号。如果第一和第二信号都处于正确状态，则两个信号都为高电平，则产生有效的输出。

6. 发明授权

US06700176B2 MOSFET anti-fuse structure and method for making same 有权
标题翻译： MOSFET反熔丝结构
公开(公告)号：US06700176B2
公开(公告)日：2004-03-02
申请号：US10197437
申请日：2002-07-18
申请人： Akira Ito , Douglas D. Smith , Myron J. Buer
发明人： Akira Ito , Douglas D. Smith , Myron J. Buer
IPC分类号： H01L27115
CPC分类号： H01L29/6659 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/7836 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
摘要翻译：反熔丝器件包括衬底和形成在衬底中的侧向间隔开的源极和漏极区域。在源区和漏区之间形成通道。在通道上形成栅极和栅极氧化物，并且在沟道中形成轻掺杂的源极和漏极延伸区域。轻掺杂的源极和漏极区域分别从源极和漏极区域延伸穿过沟道，占据通道的主要部分。通过向栅极和源极区域和漏极区域中的至少一个施加电力来执行反熔丝的编程，以分解栅极氧化物，从而最小化栅极和沟道之间的电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式