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1. 发明申请

US20070194834A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20070194834A1
公开(公告)日：2007-08-23
申请号：US11618221
申请日：2006-12-29
申请人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
发明人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07
摘要： The present invention provides a charge pump circuit capable of achieving desired boosting operation even when a high-side switch for precharge or a low-side switch for driving output is constructed by a low-withstand-voltage transistor.The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the level of an input voltage, not ground potential.
摘要翻译：本发明提供一种电荷泵电路，即使在用于预充电的高侧开关或用于驱动输出的低侧开关由低耐压晶体管构成时，也能够实现期望的升压操作。用于驱动用于预充电的高侧开关的驱动输入信号的高电平和用于响应于时钟信号驱动输出的低侧开关被设置为升压的输出电压的电平。驱动输入信号的低电平设置为输入电压的电平，而不是地电位。

2. 发明授权

US07466189B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07466189B2
公开(公告)日：2008-12-16
申请号：US11618221
申请日：2006-12-29
申请人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
发明人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： The present invention provides a charge pump circuit capable of achieving desired boosting operation even when a high-side switch for precharge or a low-side switch for driving output is constructed by a low-withstand-voltage transistor. The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the level of an input voltage, not ground potential.
摘要翻译：本发明提供一种电荷泵电路，即使在用于预充电的高侧开关或用于驱动输出的低侧开关由低耐压晶体管构成时，也能够实现期望的升压操作。用于驱动用于预充电的高侧开关的驱动输入信号的高电平和用于响应于时钟信号驱动输出的低侧开关被设置为升压的输出电压的电平。驱动输入信号的低电平设置为输入电压的电平，而不是地电位。

3. 发明授权

US07728652B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07728652B2
公开(公告)日：2010-06-01
申请号：US12331039
申请日：2008-12-09
申请人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
发明人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： The present invention provides a charge pump circuit capable of achieving desired boosting operation even when a high-side switch for precharge or a low-side switch for driving output is constructed by a low-withstand-voltage transistor. The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the level of an input voltage, not ground potential.
摘要翻译：本发明提供一种电荷泵电路，即使在用于预充电的高侧开关或用于驱动输出的低侧开关由低耐压晶体管构成时也能实现期望的升压操作。用于驱动用于预充电的高侧开关的驱动输入信号的高电平和用于响应于时钟信号驱动输出的低侧开关被设置为升压的输出电压的电平。驱动输入信号的低电平设置为输入电压的电平，而不是地电位。

4. 发明申请

US20090096508A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20090096508A1
公开(公告)日：2009-04-16
申请号：US12331039
申请日：2008-12-09
申请人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
发明人： Yasuyuki Sohara , Masayasu Tanaka , Yasuhiro Okazaki
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： The present invention provides a charge pump circuit capable of achieving desired boosting operation even when a high-side switch for precharge or a low-side switch for driving output is constructed by a low-withstand-voltage transistor. The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the level of an input voltage, not ground potential.
摘要翻译：本发明提供一种电荷泵电路，即使在用于预充电的高侧开关或用于驱动输出的低侧开关由低耐压晶体管构成时，也能够实现期望的升压操作。用于驱动用于预充电的高侧开关的驱动输入信号的高电平和用于响应于时钟信号驱动输出的低侧开关被设置为升压的输出电压的电平。驱动输入信号的低电平设置为输入电压的电平，而不是地电位。

5. 发明申请

US20060114053A1 Charge-pump-type power supply circuit 审中-公开
标题翻译：电荷泵式电源电路
公开(公告)号：US20060114053A1
公开(公告)日：2006-06-01
申请号：US11268484
申请日：2005-11-08
申请人： Yasuyuki Sohara , Masayasu Tanaka
发明人： Yasuyuki Sohara , Masayasu Tanaka
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： Two charge pump circuits are connected in a cascade manner. Each of the charge pump circuits includes two charging switches and two voltage-boosting switches. A voltage-boosting switch, provided on a side for adding a boosting voltage to a charging voltage in a second-stage charge pump circuit, includes a plurality of switches. One ends of the switches are commonly connected to a capacitor. Different boosting voltages are applied to other ends of the switches. A selecting unit selects one of the switches, during a boosting period, based on an input voltage or an output voltage to or from a first-stage charge pump circuit.
摘要翻译：两个电荷泵电路以级联方式连接。每个电荷泵电路包括两个充电开关和两个升压开关。在一侧设置有用于将升压电压加到后级电荷泵电路中的充电电压的升压开关包括多个开关。开关的一端通常连接到电容器。不同的升压电压施加到开关的另一端。选择单元在升压期间，基于来自第一级电荷泵电路的输入电压或输出电压来选择开关中的一个。

6. 发明授权

US4991075A Low-switching loss DC-DC converter 失效
标题翻译：低开关损耗DC-DC转换器
公开(公告)号：US4991075A
公开(公告)日：1991-02-05
申请号：US475979
申请日：1990-02-06
申请人： Akira Saitou , Osamu Takahashi , Seigou Tsukada , Yasuyuki Sohara , Hideki Tsuruse , Hidehiko Sugimoto
发明人： Akira Saitou , Osamu Takahashi , Seigou Tsukada , Yasuyuki Sohara , Hideki Tsuruse , Hidehiko Sugimoto
IPC分类号： H02M3/335
CPC分类号： H02M3/33538
摘要： A DC-DC converter comprises a switching element having a rise time t.sub.on and a fall time t.sub.off ; a control device for controlling the switching operation of the switching element; a transformer having a primary winding and a secondary winding, the primary winding being connected to a DC power source through the switching element, and having an open inductance L.sub.M ; an inductance coil having an inductance L connected to the secondary winding of the transformer; and a rectifying device for rectifying the output from the secondary winding of the transformer; assuming that the voltage applied to the primary winding of the transformer is E, the load current flowing through the transformer is I.sub.D, and the sum of the stray capacitance of the switching element and the distributed capacity of the windings of the transformer is C1, the following relational expressions being established:L>(E/I.sub.D)T.sub.onandL.sub.M >t.sub.off.sup.2 /.pi..sup.2 Cl
摘要翻译： DC-DC转换器包括具有上升时间吨和下降时间toff的开关元件; 控制装置，用于控制开关元件的开关动作; 具有初级绕组和次级绕组的变压器，所述初级绕组通过所述开关元件连接到DC电源，并且具有开路电感LM; 具有与变压器的次级绕组连接的电感L的电感线圈; 以及整流装置，用于对变压器的次级绕组的输出进行整流; 假设施加到变压器的初级绕组的电压为E，流过变压器的负载电流为ID，开关元件的杂散电容和变压器绕组的分布电容之和为C1，建立以下关系式：L>（E / ID）Ton和LM> toff2 / pi 2Cl

7. 发明授权

US07208997B2 Charge pump power supply circuit 失效
标题翻译：充电泵电源电路
公开(公告)号：US07208997B2
公开(公告)日：2007-04-24
申请号：US11143572
申请日：2005-06-03
申请人： Yasuyuki Sohara
发明人： Yasuyuki Sohara
IPC分类号： H02M3/18
CPC分类号： H02M3/07
摘要： In a basic circuit of a booster circuit, two charging units perform a charging operation and two boosting units perform a boosting operation (discharging operation). One of the charging units is connected to a voltage input and the other is connected to a voltage output. The charging unit that is connected to the voltage input includes three parallel connected MOS transistors Q11, Q12, and Q13, the other charging unit includes a MOS transistor Q4. One of the boosting units is connected to the voltage input and the other is connected to the voltage output. The boosting unit that is connected to the voltage input includes three parallel connected MOS transistors Q31, Q32, and Q33, the other boosting unit includes a MOS transistor Q2. Q11 and Q31 are turned ON immediately after start up, then Q12 and Q32 are turned ON and finally Q13 and Q33 are turned ON.
摘要翻译：在升压电路的基本电路中，两个充电单元进行充电操作，两个升压单元执行升压操作（放电操作）。一个充电单元连接到电压输入，另一个连接到电压输出。连接到电压输入的充电单元包括三个并联的MOS晶体管Q 11，Q 12和Q 13，另一个充电单元包括MOS晶体管Q 4。其中一个升压单元连接到电压输入，另一个连接到电压输出。连接到电压输入的升压单元包括三个并联的MOS晶体管Q 31，Q 32和Q 33，另一个升压单元包括MOS晶体管Q 2。 Q 11和Q 31在启动后立即导通，然后Q 12和Q 32导通，最后Q 13和Q 33导通。

8. 发明申请

US20050270086A1 Charge pump power supply circuit 失效
标题翻译：充电泵电源电路
公开(公告)号：US20050270086A1
公开(公告)日：2005-12-08
申请号：US11143572
申请日：2005-06-03
申请人： Yasuyuki Sohara
发明人： Yasuyuki Sohara
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/07
摘要： In a basic circuit of a booster circuit, two charging units perform a charging operation and two boosting units perform a boosting operation (discharging operation). One of the charging units is connected to voltage input and the other is connected to voltage output. The charging unit that is connected to the voltage input includes three parallel connected MOS transistors Q11, Q21, and Q13, the other charging unit includes a MOS transistor Q4. One of the boosting units is connected to voltage input and the other is connected to voltage output. The boosting unit that is connected to the voltage input includes three parallel connected MOS transistors Q31, Q32, and Q33, the other boosting unit includes a MOS transistor Q2. Q11 and Q31 are turned ON immediately after start up, then Q12 and Q22 are turned ON operation, and finally Q13 and Q23 are turned ON.
摘要翻译：在升压电路的基本电路中，两个充电单元进行充电操作，两个升压单元执行升压操作（放电操作）。一个充电单元连接到电压输入，另一个连接到电压输出。连接到电压输入的充电单元包括三个并联的MOS晶体管Q 11，Q 21和Q 13，另一个充电单元包括MOS晶体管Q 4。一个升压单元连接到电压输入，另一个连接到电压输出。连接到电压输入的升压单元包括三个并联的MOS晶体管Q 31，Q 32和Q 33，另一个升压单元包括MOS晶体管Q 2。 Q 11和Q 31在启动后立即导通，然后Q 12和Q 22导通操作，最后Q 13和Q 23导通。

9. 发明授权

US6078446A Semiconductor integrated circuit device for reading and writing 失效
标题翻译：用于读写的半导体集成电路器件
公开(公告)号：US6078446A
公开(公告)日：2000-06-20
申请号：US964902
申请日：1997-11-05
申请人： Yasuyuki Sohara
发明人： Yasuyuki Sohara
IPC分类号： G11B5/09 , G11B5/012 , G11B5/016 , G11B15/12 , G11B5/02
CPC分类号： G11B5/012 , G11B15/125 , G11B5/016
摘要： A semiconductor integrated circuit device including pairs of lower level input/output terminals 6 and 7 and pairs of high capacity input/output terminals 8 and 9, high capacity read amplifiers 10 and 11 and high capacity write drivers 14 and 15 both of which are connected to the pairs of high capacity input/output terminals 6 and 7, lower level read amplifiers 12 and 13 and the lower level write drivers 16 and 17 both of which are connected to the pairs of lower level input/output terminals 8 and 9, in which outputs from the high capacity read amplifiers 10 and 11 and outputs from the lower level read amplifiers 12 and 13 are outputted to data output terminals 36 and 37 via an amplifying circuit 35 and an output from a data input terminal 40 is outputted selectively to either one of the high capacity write drivers 14 and 15 and the lower level write drivers 16 and 17 by a write data forming circuit 39.
摘要翻译：一种半导体集成电路器件，包括一对低电平输入/输出端子6和7以及高容量输入/输出端子8和9，高容量读取放大器10和11以及两个连接的大容量写入驱动器14和15的对到成对的高容量输入/输出端子6和7，下级读取放大器12和13以及下层写入驱动器16和17两者都连接到成对的下级输入/输出端子8和9，在来自高容量读取放大器10和11的输出以及来自下级读取放大器12和13的输出经由放大电路35被输出到数据输出端36和37，并且数据输入端40的输出被选择性地输出到写入数据形成电路39是高容量写入驱动器14和15以及下位写入驱动器16和17中的一个。

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