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    • 10. 发明授权
    • Clock signal generator and data signal generator
    • 时钟信号发生器和数据信号发生器
    • US06137332A
    • 2000-10-24
    • US128789
    • 1998-08-04
    • Yoshiji InoueYasuhiro Okazaki
    • Yoshiji InoueYasuhiro Okazaki
    • H03L7/06G06F1/10H03D13/00H03L7/089H03L7/099H04L7/033H03K3/00
    • H03L7/089G06F1/10H03D13/004H03L7/0992H04L7/0331
    • A comparator compares phases of an input data supplied from an input terminal and a synchronizing clock signal output by a variable counter, and outputting a comparison result signal indicative of any of a "lead", a "lag" and a "non-detection" of the edge of the input data with respect to the up edge of the synchronizing clock signal. A state detector circuit detects the numbers of "leads" and "lags" in comparison result signals output by the comparator, and outputting a state detected signal indicative of any of "the number of leads is larger", "the number of lags is larger" and "the number of leads is equal to the number of lags". A dividing ratio selection circuit outputs a dividing ratio signal indicative of any of a "dividing ratio smaller than a reference dividing ratio", a "dividing ratio greater than the reference dividing ratio" and the "reference dividing ratio", based on the comparison result signals output by the comparator and state detected signals output by the state detector circuit. A variable counter divides the frequency of a reference clock signal in response to the dividing ratio signal output by the dividing ratio selection circuit and outputs the result of the division to the comparator and an output terminal.
    • 比较器比较从输入端提供的输入数据和由可变计数器输出的同步时钟信号的相位,并输出指示“引导”,“滞后”和“非检测” 输入数据的边缘相对于同步时钟信号的上升沿。 状态检测器电路检测由比较器输出的比较结果信号中的“引线”和“滞后”数,并且输出表示“引线数量”中的任何一个的状态检测信号,“滞后数较大 “和”潜在客户的数量等于滞后数“。 分频比选择电路根据比较结果输出表示“分压比小于基准分压比”,“分压比大于基准分压比”和“基准分压比”的分频比信号 由比较器输出的信号和由状态检测器电路输出的状态检测信号。 可变计数器根据由分频比选择电路输出的分频比信号来分频参考时钟信号的频率,并将分频结果输出到比较器和输出端。