专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07795092B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07795092B2
公开(公告)日：2010-09-14
申请号：US12132450
申请日：2008-06-03
申请人： Yasuyuki Matsuoka , Masaru Kito , Hideaki Aochi , Takayuki Okamura
发明人： Yasuyuki Matsuoka , Masaru Kito , Hideaki Aochi , Takayuki Okamura
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory device includes gate electrodes extending in a first direction above a surface of a substrate. The semiconductor memory device also includes a reinforcement insulation film formed in a line shape and extending in a second direction crossing the gate electrodes in a plane view viewed from above the surface of the substrate, and connected to adjacent gate electrodes. Further, the semiconductor memory device includes an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.
摘要翻译：半导体存储器件包括沿基板表面的第一方向延伸的栅电极。半导体存储器件还包括形成为线形并且在从基板的表面上方观察的平面图中的与栅电极交叉的第二方向上延伸并且连接到相邻栅电极的加强绝缘膜。此外，半导体存储器件包括设置在相邻栅电极之间并且内部具有空隙的层间电介质膜。

2. 发明申请

US20090001444A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090001444A1
公开(公告)日：2009-01-01
申请号：US12132450
申请日：2008-06-03
申请人： Yasuyuki MATSUOKA , Masaru Kito , Hideaki Aochi , Takayuki Okamura
发明人： Yasuyuki MATSUOKA , Masaru Kito , Hideaki Aochi , Takayuki Okamura
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： This disclosure concerns a semiconductor memory device comprising a plurality of gate electrodes extending to a first direction; a reinforced insulation film extending to a second direction crossing the first direction, and connected to the adjacent gate electrodes; and an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.
摘要翻译：本公开涉及包括延伸到第一方向的多个栅电极的半导体存储器件; 加强绝缘膜延伸到与第一方向交叉的第二方向，并且连接到相邻的栅电极; 以及设置在相邻的栅电极之间并且内部具有空隙的层间绝缘膜。

3. 发明申请

US20080246168A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080246168A1
公开(公告)日：2008-10-09
申请号：US12059280
申请日：2008-03-31
申请人： Masaru Kito , Hideaki Aochi , Takayuki Okamura
发明人： Masaru Kito , Hideaki Aochi , Takayuki Okamura
IPC分类号： H01L21/308 , H01L23/52
CPC分类号： H01L21/3086 , H01L21/3088 , H01L27/105 , H01L27/1052 , H01L27/11524
摘要： A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.
摘要翻译：半导体器件包括半导体层，该半导体层包括在第一方向上延伸的多个平行的线性直线部分。该层还包括多个连接部分，每个连接部分具有在第一方向上的宽度，足以在其中形成可接线的触点，并且布置成在第二方向上在相邻的直部分之间连接。连接部具有与平行于第二方向的第一直线对准的各自的端部。

4. 发明授权

US07737041B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07737041B2
公开(公告)日：2010-06-15
申请号：US12059280
申请日：2008-03-31
申请人： Masaru Kito , Hideaki Aochi , Takayuki Okamura
发明人： Masaru Kito , Hideaki Aochi , Takayuki Okamura
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L27/105 , H01L27/1052 , H01L27/11524
摘要： A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.
摘要翻译：半导体器件包括半导体层，该半导体层包括在第一方向上延伸的多个平行的线性直线部分。该层还包括多个连接部分，每个连接部分具有在第一方向上的宽度，足以在其中形成可接线的触点，并且布置成在第二方向上在相邻的直部分之间连接。连接部具有与平行于第二方向的第一直线对准的各自的端部。

5. 发明申请

US20100219538A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100219538A1
公开(公告)日：2010-09-02
申请号：US12776454
申请日：2010-05-10
申请人： Masaru KITO , Hideaki Aochi , Takayuki Okamura
发明人： Masaru KITO , Hideaki Aochi , Takayuki Okamura
IPC分类号： H01L23/538
CPC分类号： H01L21/3086 , H01L21/3088 , H01L27/105 , H01L27/1052 , H01L27/11524
摘要： A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.
摘要翻译：半导体器件包括半导体层，该半导体层包括在第一方向上延伸的多个平行的线性直线部分。该层还包括多个连接部分，每个连接部分具有在第一方向上的宽度，足以在其中形成可接线的触点，并且布置成在第二方向上在相邻的直部分之间连接。连接部具有与平行于第二方向的第一直线对准的各自的端部。

6. 发明授权

US08598649B2 Nonvolatile semiconductor memory device and method for manufacturing same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08598649B2
公开(公告)日：2013-12-03
申请号：US12792378
申请日：2010-06-02
申请人： Takayuki Okamura , Noboru Ooike , Wataru Sakamoto , Takashi Izumida
发明人： Takayuki Okamura , Noboru Ooike , Wataru Sakamoto , Takashi Izumida
IPC分类号： H01L29/792 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11565 , H01L21/28282 , H01L27/11568
摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.
摘要翻译：根据实施例的非易失性半导体存储器件包括：半导体衬底，其具有被分隔成沿第一方向延伸的多个半导体部分的上部; 设置在半导体部分上的电荷存储膜; 字线电极，其设置在所述半导体基板上并沿与所述第一方向交叉的第二方向延伸; 以及一对选择栅电极，其设置在所述半导体基板上的所述字线电极的所述第一方向的两侧，并且沿所述第二方向延伸，所述半导体部分的每个的角部与所述选择中的每一个之间的最短距离栅电极比与半导体部分的角部和字线电极之间的平行于第二方向的截面中的最短距离更长。

7. 发明授权

US07936005B2 Semiconductor memory device including laminated gate having electric charge accumulating layer and control gate and method of manufacturing the same 有权
标题翻译：包括具有电荷累积层和控制栅极的层叠栅极的半导体存储器件及其制造方法
公开(公告)号：US07936005B2
公开(公告)日：2011-05-03
申请号：US12473709
申请日：2009-05-28
申请人： Takayuki Okamura
发明人： Takayuki Okamura
IPC分类号： H01L29/792
CPC分类号： H01L27/11568
摘要： A semiconductor memory device includes a first active region, a second active region, an element isolation region, memory cell transistors. Each of memory cell transistors includes a laminated gate and a first impurity diffusion layer functioning as a source and a drain. The laminated gate includes a first insulating film, a second insulating film, and a control gate electrode. The second insulating film is commonly connected between the plurality of memory cell transistors to step over the element isolation region and is in contact with an upper surface of the element isolation region. An upper surface of the element isolation region is higher than a bottom surface of the first insulating film and is located under the upper surface of the first insulating film.
摘要翻译：半导体存储器件包括第一有源区，第二有源区，元件隔离区，存储单元晶体管。每个存储单元晶体管包括层叠栅极和用作源极和漏极的第一杂质扩散层。层叠栅极包括第一绝缘膜，第二绝缘膜和控制栅电极。第二绝缘膜通常连接在多个存储单元晶体管之间，以跨越元件隔离区并与元件隔离区的上表面接触。元件隔离区的上表面高于第一绝缘膜的底面，位于第一绝缘膜的上表面的下方。

8. 发明授权

US4412022A Polyurethane coating compositions prepared from a polymeric diol, an alicyclic diisocyanate, an alicyclic diamine and either hydrazine or isophthalic acid dihydrazide 失效
标题翻译：由聚合二醇，脂环族二异氰酸酯，脂环族二胺和肼或间苯二甲酸二酰肼制备的聚氨酯涂料组合物
公开(公告)号：US4412022A
公开(公告)日：1983-10-25
申请号：US374923
申请日：1982-05-05
申请人： Koji Hirai , Kenji Shirano , Takayuki Okamura
发明人： Koji Hirai , Kenji Shirano , Takayuki Okamura
IPC分类号： C08G18/10 , C08G18/75 , C08L75/08
CPC分类号： C08G18/75 , C08G18/10
摘要： Polyurethane compositions comprising a polyurethane synthesized by reacting a diol, a specific alicyclic diisocyanate, a specific alicyclic diamine and hydrazine or isophthalic acid dihydrazide in specific proportions and a solvent therefor have good solution stability and, when applied as coating compositions, give coats with good light stability, good surface properties, high softening points and sufficient flexibility at low temperatures.
摘要翻译：包含通过使二醇，特定脂环族二异氰酸酯，特定脂环族二胺和特定比例的肼或间苯二甲酸二酰肼以及其溶剂反应合成的聚氨酯的聚氨酯组合物具有良好的溶液稳定性，并且当作为涂料组合物涂布时，稳定性好，表面性能好，软化点高，在低温下具有足够的柔韧性。

9. 发明申请

US20090218607A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20090218607A1
公开(公告)日：2009-09-03
申请号：US12393186
申请日：2009-02-26
申请人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
发明人： Takayuki Toba , Takayuki Okamura , Moto Yabuki
IPC分类号： H01L29/792 , H01L29/00 , H01L21/336
CPC分类号： H01L27/11573
摘要： A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.
摘要翻译：本发明的一个方面的非易失性半导体存储器包括存储单元形成区域中的存储单元，并且在选择栅极形成区域中选择栅极晶体管。每个存储单元具有形成在半导体衬底中的两个第一扩散层，形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷存储层，形成在电荷存储层上的第一中间绝缘膜和第一栅电极，形成在第一中间绝缘膜上。每个选择晶体管具有形成在半导体衬底中的两个第二扩散层，形成在半导体衬底上的第二栅极绝缘膜，与第二栅极绝缘膜直接接触形成并具有与第一中间层相同结构的第二中间绝缘膜绝缘膜和形成在第二中间绝缘膜上的第二栅电极。

10. 发明授权

US4367307A Polyurethane composition having good light resistance 失效
标题翻译：聚氨酯组合物具有良好的耐光性
公开(公告)号：US4367307A
公开(公告)日：1983-01-04
申请号：US250554
申请日：1981-04-03
申请人： Koji Hirai , Kenji Shirano , Kazuo Hara , Takayuki Okamura
发明人： Koji Hirai , Kenji Shirano , Kazuo Hara , Takayuki Okamura
IPC分类号： C08G18/00 , C08G18/10 , C08G18/12 , C08G18/40 , C08G18/48 , C08G18/65 , C08G18/66 , C08G18/73 , C08G18/75 , C08K5/00 , D06N3/00 , D06N3/14 , C08L75/08
CPC分类号： D06N3/14 , C08G18/10 , C08G18/12 , C08G18/4018 , C08G18/4833 , C08K5/0041 , D06N3/0065
摘要： A polyurethane composition comprising a polyurethane and at least one dye selected from the group consisting of metal complex dyes, vat dyes, sulfur dyes and acid dyes. The polyurethane is synthesized by the reaction of a polymeric diol containing a polyoxyethylene chain as a minor proportion, an alicyclic diisocyanate, an alicyclic diamine and hydrazine in particular proportions. This polyurethane composition is little susceptible to deterioration by light and is suitable for use as a component of artificial leather or as a coating material for fabrics.
摘要翻译：一种聚氨酯组合物，其包含聚氨酯和至少一种选自金属络合物染料，还原染料，硫化染料和酸性染料的染料。聚氨酯通过含有少量聚氧乙烯链的聚合二醇，脂环族二异氰酸酯，脂环族二胺和肼以特定比例的反应合成。该聚氨酯组合物几乎不受光的劣化的影响，适用于人造革的组分或作为织物的涂料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式