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1. 发明申请

US20060030086A1 Method of manufacturing thin film transistor 有权
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US20060030086A1
公开(公告)日：2006-02-09
申请号：US11196574
申请日：2005-08-04
申请人： Yasuyoshi Itoh , Takeshi Kubota , Toru Takeguchi
发明人： Yasuyoshi Itoh , Takeshi Kubota , Toru Takeguchi
IPC分类号： H01L21/84 , H01L21/425
CPC分类号： H01L29/78621 , H01L21/268 , H01L29/66757 , H01L29/78603 , H01L29/78627
摘要： Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.
摘要翻译：包含在半导体层中的杂质离子通过在形成源极 - 漏极区域之后从透明衬底的背面照射激光而从栅电极向下扩散。因此，形成GOLD结构。因此，通过执行较少数量的处理来形成GOLD结构。此外，通过防止左右LDD区域之间的不对称性可以抑制特性的变化。

2. 发明授权

US07148091B2 Method of manufacturing thin film transistor 有权
公开(公告)号：US07148091B2
公开(公告)日：2006-12-12
申请号：US11196574
申请日：2005-08-04
申请人： Yasuyoshi Itoh , Takeshi Kubota , Toru Takeguchi
发明人： Yasuyoshi Itoh , Takeshi Kubota , Toru Takeguchi
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L29/78621 , H01L21/268 , H01L29/66757 , H01L29/78603 , H01L29/78627
摘要： Impurity ions contained in a semiconductor layer are diffused downwardly from a gate electrode by irradiating laser light from the back surface of a transparent substrate after source-drain regions are formed. Thus, a GOLD structure is formed. Consequently, the GOLD structure is formed by performing a smaller number of processes. Also, variation in characteristics can be suppressed by preventing occurrence of asymmetry between left and right LDD regions.

3. 发明授权

US08908117B2 Thin film transistor array substrate and liquid crystal display apparatus comprising a transparent conductive film pattern having a first type pattern and a second type pattern 有权
标题翻译：薄膜晶体管阵列基板和包括具有第一类型图案和第二类型图案的透明导电膜图案的液晶显示装置
公开(公告)号：US08908117B2
公开(公告)日：2014-12-09
申请号：US13281893
申请日：2011-10-26
申请人： Masami Hayashi , Osamu Miyagawa , Toru Takeguchi , Shinichi Yano , Yasuyoshi Itoh , Shingo Nagano
发明人： Masami Hayashi , Osamu Miyagawa , Toru Takeguchi , Shinichi Yano , Yasuyoshi Itoh , Shingo Nagano
IPC分类号： G02F1/136 , G02F1/1343 , G02F1/1345 , H01L27/12 , G02F1/1362
CPC分类号： H01L27/124 , G02F1/13452 , G02F1/136286
摘要： A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.
摘要翻译：具有阵列区域和框架区域的本发明的薄膜晶体管阵列基板，薄膜晶体管阵列基板包括：薄膜晶体管; 由与同层的源极和漏极相同的材料形成的上部金属图案; 透明导电膜图案; 和上层绝缘膜，其中透明导电膜图案具有：从顶侧观察设置为位于电极图案的图案和金属图案的图案之一内的第一类型透明导电膜图案，并且不覆盖电极图案或金属图案的图案端面; 以及第二类型的透明导电膜图案，设置成从顶侧观察到从图案的至少一部分的内侧伸出并覆盖图案端面。

4. 发明授权

US07709841B2 Thin film transistor having an island like semiconductor layer on an insulator 失效
标题翻译：在绝缘体上具有岛状半导体层的薄膜晶体管
公开(公告)号：US07709841B2
公开(公告)日：2010-05-04
申请号：US11420956
申请日：2006-05-30
申请人： Yasuyoshi Itoh , Toru Takeguchi
发明人： Yasuyoshi Itoh , Toru Takeguchi
IPC分类号： H01L29/04
CPC分类号： H01L29/78675 , H01L27/1296 , H01L29/78666
摘要： An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.
摘要翻译：在绝缘基板的主表面上形成岛状半导体层。岛状半导体层的侧壁基本上垂直于绝缘基板。沿半导体层的侧壁形成绝缘膜。绝缘膜形成为包括倾斜面，并且具有从半导体层的侧壁测量的宽度随着与底部距离的增加而减小的截面形状。由于包含绝缘膜，可以在半导体层上形成具有良好阶梯覆盖的栅极绝缘膜，以防止导致栅电极断开的可能性。此外，其中形成沟道区的半导体层的一部分的厚度是均匀的，以获得稳定的晶体管特性。

5. 发明申请

US20070034871A1 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20070034871A1
公开(公告)日：2007-02-15
申请号：US11420956
申请日：2006-05-30
申请人： Yasuyoshi Itoh , Toru Takeguchi
发明人： Yasuyoshi Itoh , Toru Takeguchi
IPC分类号： H01L29/04
CPC分类号： H01L29/78675 , H01L27/1296 , H01L29/78666
摘要： An island-like semiconductor layer is formed on a main surface of an insulating substrate. A side wall of the island-like semiconductor layer is made substantially perpendicular to the insulating substrate. An insulating film is formed along the side wall of the semiconductor layer. The insulating film is formed to include a slanted face and have a sectional shape in which a width measured from the side wall of the semiconductor layer decreases as a distance to a bottom increases. A gate insulating film can be formed on the semiconductor layer with good step coverage because of inclusion of the insulating film, to preclude a possibility of causing disconnection of a gate electrode. Also, a thickness of a portion of the semiconductor layer in which a channel region is formed is uniform, to obtain stable transistor characteristics.
摘要翻译：在绝缘基板的主表面上形成岛状半导体层。岛状半导体层的侧壁基本上垂直于绝缘基板。沿半导体层的侧壁形成绝缘膜。绝缘膜形成为包括倾斜面，并且具有从半导体层的侧壁测量的宽度随着与底部距离的增加而减小的截面形状。由于包含绝缘膜，可以在半导体层上形成具有良好阶梯覆盖的栅极绝缘膜，以防止导致栅电极断开的可能性。此外，其中形成沟道区的半导体层的一部分的厚度是均匀的，以获得稳定的晶体管特性。

6. 发明申请

US20120113376A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY APPARATUS 有权
标题翻译：薄膜晶体管阵列和液晶显示设备
公开(公告)号：US20120113376A1
公开(公告)日：2012-05-10
申请号：US13281893
申请日：2011-10-26
申请人： Masami HAYASHI , Osamu Miyagawa , Toru Takeguchi , Shinichi Yano , Yasuyoshi Itoh , Shingo Nagano
发明人： Masami HAYASHI , Osamu Miyagawa , Toru Takeguchi , Shinichi Yano , Yasuyoshi Itoh , Shingo Nagano
IPC分类号： G02F1/1343 , H01L29/786
CPC分类号： H01L27/124 , G02F1/13452 , G02F1/136286
摘要： A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.
摘要翻译：具有阵列区域和框架区域的本发明的薄膜晶体管阵列基板，薄膜晶体管阵列基板包括：薄膜晶体管; 由与同层的源极和漏极相同的材料形成的上部金属图案; 透明导电膜图案; 和上层绝缘膜，其中透明导电膜图案具有：从顶侧观察设置为位于电极图案的图案和金属图案的图案之一内的第一类型透明导电膜图案，并且不覆盖电极图案或金属图案的图案端面; 以及第二类型的透明导电膜图案，设置成从顶侧观察到从图案的至少一部分的内侧伸出并覆盖图案端面。

7. 发明授权

US07799621B2 Method of manufacturing thin film transistor array substrate and display device 有权
标题翻译：制造薄膜晶体管阵列基板和显示装置的方法
公开(公告)号：US07799621B2
公开(公告)日：2010-09-21
申请号：US12266064
申请日：2008-11-06
申请人： Yasuyoshi Itoh , Toshio Araki
发明人： Yasuyoshi Itoh , Toshio Araki
IPC分类号： H01L29/786
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film.
摘要翻译：根据本发明的制造薄膜晶体管阵列基板的方法包括：形成由第一导电膜制成的图案; 以所述顺序层叠栅极绝缘膜，半导体层和抗蚀剂; 在厚度方向上形成具有台阶结构的抗蚀剂图案; 通过使用抗蚀剂图案形成第一导电膜的暴露区域和半导体层的图案; 在所述第一导电膜的暴露区域中形成与所述第一导电膜接触的第二导电膜形成的图案; 以及形成由第三导电膜制成的图案。第一导电膜形成栅电极，第二导电膜形成源电极和漏电极。第三导电膜形成像素电极，第二导电膜涂覆有上层膜。

8. 发明授权

US07397063B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07397063B2
公开(公告)日：2008-07-08
申请号：US10898360
申请日：2004-07-26
申请人： Yasuyoshi Itoh , Kaoru Motonami
发明人： Yasuyoshi Itoh , Kaoru Motonami
IPC分类号： H01L29/04
CPC分类号： H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , Y10S257/913
摘要： A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.
摘要翻译：半导体器件包括用作具有绝缘表面的基板的玻璃基板和位于与该玻璃基板重叠的位置的硅层。硅层包括无定形吸气区域。优选地，硅层包括用作有源元件区域的主区域，并且除了主区域之外的硅层的剩余部分中优选包含吸杂区域。优选地，硅层可以包括用作薄膜晶体管的有源区的部分。

9. 发明授权

US06867455B2 Semiconductor device with a metal insulator semiconductor transistor 失效
标题翻译：具有金属绝缘体半导体晶体管的半导体器件
公开(公告)号：US06867455B2
公开(公告)日：2005-03-15
申请号：US10600344
申请日：2003-06-23
申请人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
发明人： Yasuyoshi Itoh , Shuuichi Ueno , Haruo Furuta , Natsuo Ajika
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66833 , H01L21/26586 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/42368 , H01L29/513 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7923
摘要： A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.
摘要翻译：一种能够将多位信息保持在一个存储单元中的半导体器件，以及半导体器件的制造方法。在MONOS晶体管的沟道部分中形成沟槽。然后，使介入沟槽的栅极绝缘膜的氮化硅膜中的源极侧部分和漏极侧部分作为能够保持电荷的第一和第二电荷保持部分起作用。在第一电荷被捕获在漏极侧并且第二电荷被捕获在源极侧的情况下，沟槽中的栅电极的一部分用作屏蔽。如果向栅电极施加固定电位，则第二电荷保持部不受第一电荷引起的电场的影响，从而不抑制第二电荷的捕获。

10. 发明授权

US06548871B1 Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer 失效
标题翻译：半导体器件通过在相同的线层中形成第一层布线和栅极上电极来实现缩短的布线长度并减少布线延迟
公开(公告)号：US06548871B1
公开(公告)日：2003-04-15
申请号：US09543349
申请日：2000-04-05
申请人： Katsuyuki Horita , Takashi Kuroi , Yasuyoshi Itoh , Katsuomi Shiozawa
发明人： Katsuyuki Horita , Takashi Kuroi , Yasuyoshi Itoh , Katsuomi Shiozawa
IPC分类号： H01L2976
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/823475 , H01L23/522 , H01L23/535 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
摘要翻译：属于彼此相邻的分离元件的两个源极/漏极区域（20）通过与形成栅电极的一部分的金属层（10）的高度相同的高度的金属层（14）连接。在制造过程中，绝缘层（8）由除两个绝缘层（7）和（16）之外的其它材料制成。两个绝缘层（7）和（16）作为用于将金属层（10），（14）和（15）埋入其中并由相同材料制成的模具。因此，金属层（14）可以形成在与金属层（10）的高度相同的高度。因此，通过布置在较短距离处的布线而连接的部分被连接，同时降低布线能力。

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