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1. 发明授权

US4636833A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4636833A
公开(公告)日：1987-01-13
申请号：US590870
申请日：1984-03-19
申请人： Yasushiro Nishioka , Noriyuki Homma , Noriyuki Sakuma , Kiichiro Mukai
发明人： Yasushiro Nishioka , Noriyuki Homma , Noriyuki Sakuma , Kiichiro Mukai
IPC分类号： G11C11/411 , H01L21/822 , H01L21/8229 , H01L27/04 , H01L27/07 , H01L27/102 , H01L23/48
CPC分类号： H01L27/0788 , H01L27/1025
摘要： A semiconductor device comprising a first electrode, a dielectric film and a second electrode which are stacked and formed on a semiconductor layer with the second electrode in contact with the semiconductor layer. A diode is formed of the second electrode and the semiconductor layer, and a capacitor is formed of the first electrode, the dielectric film and the second electrode.
摘要翻译：一种半导体器件，包括第一电极，电介质膜和第二电极，所述第一电极，电介质膜和第二电极层叠并形成在半导体层上，其中第二电极与半导体层接触。二极管由第二电极和半导体层形成，电容器由第一电极，电介质膜和第二电极形成。

2. 发明授权

US5324982A Semiconductor memory device having bipolar transistor and structure to avoid soft error 失效
标题翻译：半导体存储器件具有双极晶体管和结构，以避免软错误
公开(公告)号：US5324982A
公开(公告)日：1994-06-28
申请号：US769680
申请日：1991-10-02
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/04 , H01L29/70
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

3. 发明授权

US4986666A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4986666A
公开(公告)日：1991-01-22
申请号：US277261
申请日：1988-11-29
申请人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
发明人： Noriyuki Homma , Hisayuki Higuchi , Yoji Idei , Hiroaki Nambu , Yoshiaki Sakurai
IPC分类号： G11C7/06 , G11C7/10 , G11C8/10 , G11C11/416
CPC分类号： G11C7/1057 , G11C11/416 , G11C7/062 , G11C7/065 , G11C7/1039 , G11C7/1051 , G11C8/10
摘要： A semiconductor memory device capable of operating at high speeds, and a sense circuit and a decoder circuit that can be suitably used for the memory device. A latch function is imparted to at least either one of the decoder circuit or the sense circuit in the semiconductor memory device.
摘要翻译：能够高速运行的半导体存储器件，以及适用于存储器件的读出电路和解码器电路。锁存功能被赋予半导体存储器件中的解码器电路或感测电路中的至少一个。

4. 发明授权

US4829361A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4829361A
公开(公告)日：1989-05-09
申请号：US120921
申请日：1987-11-16
申请人： Kazuhiko Sagara , Tohru Nakamura , Kazuo Nakazato , Tokuo Kure , Kiyoji Ikeda , Noriyuki Homma
发明人： Kazuhiko Sagara , Tohru Nakamura , Kazuo Nakazato , Tokuo Kure , Kiyoji Ikeda , Noriyuki Homma
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8229 , H01L21/8234 , H01L27/088 , H01L27/10 , H01L27/102 , H01L29/732
CPC分类号： H01L27/1025 , H01L21/74 , H01L21/762 , Y10S257/906
摘要： A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.
摘要翻译：一种半导体器件，其中在掩埋层和外延层之间提供掺杂有杂质的层，所述层掺杂有与所述掩埋层和所述外延层的导电类型相反的导电类型的杂质，施加反向偏置电压掺杂有杂质的掩埋层和层，外延层的侧表面被绝缘体包围。这有助于有效地防止外延层中形成的元件受到α-粒子的影响，并且极大地提高了半导体器件的可靠性。

5. 发明授权

US4461992A Temperature-compensated current source circuit and a reference voltage generating circuit using the same 失效
标题翻译：温度补偿电流源电路和使用其的参考电压发生电路
公开(公告)号：US4461992A
公开(公告)日：1984-07-24
申请号：US367676
申请日：1982-04-12
申请人： Kunihiko Yamaguchi , Noriyuki Homma
发明人： Kunihiko Yamaguchi , Noriyuki Homma
IPC分类号： G05F1/56 , G05F1/567 , G05F3/30 , G05F3/20
CPC分类号： G05F1/567 , G05F3/30 , Y10S323/907
摘要： A current source circuit includes a first and a second transistor connected at the collector to a common load resistor. In the current source circuit, the emiiters of the first and second transistors are connected to a negative power source through different current restricting resistors. The base of the first transistor is biased by a series circuit including two diodes. The temperature coefficients of the collector currents of the first and second transistors are offset, so that the temperature-compensated current flows into the load resistor.
摘要翻译：电流源电路包括在集电极处连接到公共负载电阻器的第一和第二晶体管。在电流源电路中，第一和第二晶体管的发射器通过不同的电流限制电阻器连接到负电源。第一晶体管的基极由包括两个二极管的串联电路偏置。第一和第二晶体管的集电极电流的温度系数偏移，使得温度补偿电流流入负载电阻器。

6. 发明授权

US06864559B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06864559B2
公开(公告)日：2005-03-08
申请号：US10377717
申请日：2003-03-04
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/00
CPC分类号： H01L27/0623 , H01L27/0214 , H01L27/0218 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

7. 发明授权

US5497023A Semiconductor memory device having separately biased wells for isolation 失效
标题翻译：半导体存储器件具有单独偏置的阱用于隔离
公开(公告)号：US5497023A
公开(公告)日：1996-03-05
申请号：US352238
申请日：1994-12-08
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikasu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikasu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

8. 发明授权

US5448527A Decoder and driver for use in a semiconductor memory 失效
标题翻译：用于半导体存储器的解码器和驱动器
公开(公告)号：US5448527A
公开(公告)日：1995-09-05
申请号：US149936
申请日：1993-11-10
申请人： Hiroaki Nambu , Noriyuki Homma , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Takesi Kusunoki
发明人： Hiroaki Nambu , Noriyuki Homma , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Takesi Kusunoki
IPC分类号： G11C11/413 , G11C8/08 , G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A decoder formed of multiple circuit blocks each including bipolar transistors Q1 and Q2 having their collectors connected to resistors R1 and R2, respectively, a bipolar transistor Q3 having its collector supplied with a power voltage, and a current source I1 connected commonly to the emitters of Q1-Q3. This circuit configuration permits the decoder and BiCMOS memories using it to operate with a low supply voltage.
摘要翻译：由多个电路块形成的解码器，每个电路块分别包括双极晶体管Q1和Q2，它们的集电极分别连接到电阻器R1和R2，其集电极被提供有电源电压的双极晶体管Q3和共同连接到发射极的发射极 Q1-Q3。该电路配置允许使用它的解码器和BiCMOS存储器以低电源电压工作。

9. 发明授权

US5163022A Semiconductor cell memory with current sensing 失效
标题翻译：具有电流检测功能的半导体单元存储器
公开(公告)号：US5163022A
公开(公告)日：1992-11-10
申请号：US827873
申请日：1992-01-30
申请人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
发明人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
IPC分类号： G11C7/06 , G11C11/411 , G11C11/412 , G11C11/416 , G11C11/419
CPC分类号： G11C11/4113 , G11C11/412 , G11C11/416 , G11C11/419 , G11C7/062
摘要： The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.
摘要翻译：本公开包括将电流IR馈送到仅选择的BIT线，或者将电流IR瞬时馈送到仅从未选择状态切换到选定状态的BIT线; 以及读出放大器，用于检测在所选择的BIT行中流动的电流之间的差以读出存储的信息，其中当前的IR和单元电流Icell具有IR> Icell的关系。 BiC MOS存储器具有高速度，低功耗和高集成度。在存储单元和BIT线之间提供二极管。

10. 发明授权

US07123534B2 Semiconductor memory device having short refresh time 失效
标题翻译：具有短刷新时间的半导体存储器件
公开(公告)号：US07123534B2
公开(公告)日：2006-10-17
申请号：US10943895
申请日：2004-09-20
申请人： Hiroaki Nambu , Noriyuki Homma
发明人： Hiroaki Nambu , Noriyuki Homma
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/4085 , G11C11/4096 , G11C2211/4065
摘要： A semiconductor memory device in which memory cells are arranged at intersections between the word lines and the bit lines includes a control unit for selecting, in a second half of a cycle in which a first word line is selected from the word lines to conduct a read or write operation for a first memory cell coupled with the first word line, a second word line other than the first word line and refreshing memory cells corresponding to the second word line. The memory cell includes an amplifier section including two driver transistors of which gate and drain electrodes are respectively cross-coupled with each other and a switch section including selector transistors coupling the amplifier section with the bit lines according to a selection signal on the bit line. Either one of each transistor and each selector transistor is an n-channel transistor or a p-type transistor.
摘要翻译：一种半导体存储器件，其中存储器单元布置在字线和位线之间的交叉处，包括控制单元，用于在从字线中选择第一字线以进行读取的周期的后半段中进行选择或与第一字线耦合的第一存储单元的写入操作，除第一字线以外的第二字线和对应于第二字线的刷新存储单元。存储单元包括放大器部分，其包括两个驱动晶体管，栅极和漏极彼此分别交叉耦合;以及开关部分，包括根据位线上的选择信号将放大器部分与位线耦合的选择晶体管。每个晶体管和每个选择晶体管中的任一个是n沟道晶体管或p型晶体管。

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