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1. 发明授权

US07835169B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07835169B2
公开(公告)日：2010-11-16
申请号：US12368622
申请日：2009-02-10
申请人： Yasuo Murakuki , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yoshiaki Nakao
发明人： Yasuo Murakuki , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yoshiaki Nakao
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.
摘要翻译：半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括以矩阵图案排列的多个存储单元，以及多个存储单元阵列共享的单元板板线，每个单元板线对应于存储单元的行和每个单元格板线连接到相应行之一的存储单元。每个存储单元阵列包括多个字线，每个字线对应于存储单元阵列中存储单元的行中的每一行。连接到每个单元格板行的存储单元的数量大于连接到与每个单元格板行相对应的一个字线的存储单元的数量。

2. 发明申请

US20100023840A1 ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM 审中-公开
标题翻译： ECC电路，半导体存储器件，存储器系统
公开(公告)号：US20100023840A1
公开(公告)日：2010-01-28
申请号：US12480294
申请日：2009-06-08
申请人： Yoshiaki Nakao , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yasuo Murakuki
发明人： Yoshiaki Nakao , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yasuo Murakuki
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/13 , G06F11/1008 , H03M13/19
摘要： A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section.
摘要翻译：校正子产生部分从具有数据位d位和奇偶校验位k位的输入数据生成校正子。校正子表存储指示在输入数据中没有发生错误的校正子模式和指示错误位置的校正子模式。比较部分将由校正子产生部分产生的综合征与综合征表中的综合征模式进行比较，当不存在匹配该综合征的综合征模式时，输出匹配信号，并且当不存在与该综合征相匹配的症状模式时，输出不匹配信号。误差校正部分根据比较部分的匹配信号校正输入数据中的误差。

3. 发明申请

US20080028132A1 Non-volatile storage device, data storage system, and data storage method 审中-公开
标题翻译：非易失性存储设备，数据存储系统和数据存储方法
公开(公告)号：US20080028132A1
公开(公告)日：2008-01-31
申请号：US11798679
申请日：2007-05-16
申请人： Masanori Matsuura , Yasushi Gohou , Shunichi Iwanari , Yoshiaki Nakao , Hisakazu Kotani , Junichi Kato , Satoshi Mishima , Motonobu Nishimura , Toshiki Mori
发明人： Masanori Matsuura , Yasushi Gohou , Shunichi Iwanari , Yoshiaki Nakao , Hisakazu Kotani , Junichi Kato , Satoshi Mishima , Motonobu Nishimura , Toshiki Mori
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F13/1668 , G06F2212/7203 , G11C16/10
摘要： A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.
摘要翻译：非易失性存储装置包括：每单位区域写入数据的非易失性存储器;以及用于控制将数据写入非易失性存储器的存储器控制器。存储器控制器包括用于保存从设备外部输入的数据的第一存储部分，用于将由第一存储部分保存并且其数量对应于单位区域的数据写入到非易失性存储器中的第一控制部分以单位面积为单位的区域，以及将由第一存储部保持的数量小于单位面积的写入数据写入到第二存储部中，以及第二控制部，用于写入由第二存储器部分进入非易失性存储器。

4. 发明申请

US20090210612A1 MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：内存控制器，非易失性存储器件和非易失性存储器系统
公开(公告)号：US20090210612A1
公开(公告)日：2009-08-20
申请号：US12282693
申请日：2007-03-12
申请人： Masahiro Nakanishi , Masayuki Toyama , Yutaka Nakamura , Yasushi Gohou , Masanori Matsuura , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shunichi Iwanari , Shinichi Tokumitsu
发明人： Masahiro Nakanishi , Masayuki Toyama , Yutaka Nakamura , Yasushi Gohou , Masanori Matsuura , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shunichi Iwanari , Shinichi Tokumitsu
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed.
摘要翻译：在逻辑扇区的重写处理中，传送的逻辑扇区的数据被临时存储在存储缓冲器中。当缓冲存储器已经完全填满数据时，数据被写入闪存。在包括具有大于来自外部的最小写入单位（扇区）的容量的写入单元（页）的闪存的重写处理中，可以减少撤离处理的执行次数并且可以执行快速数据重写。因此，可以使以扇区为单位重写的旧数据的撤离处理合理化，并提高数据重写速度。

5. 发明申请

US20080313391A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20080313391A1
公开(公告)日：2008-12-18
申请号：US12136340
申请日：2008-06-10
申请人： Shunichi Iwanari , Hisakazu Kotani , Masanori Matsuura
发明人： Shunichi Iwanari , Hisakazu Kotani , Masanori Matsuura
IPC分类号： G06F12/02
CPC分类号： G11C16/26 , G11C7/1039 , G11C7/1051 , G11C7/1063
摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.
摘要翻译：一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

6. 发明授权

US07991945B2 Semiconductor memory device and semiconductor device 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US07991945B2
公开(公告)日：2011-08-02
申请号：US12136340
申请日：2008-06-10
申请人： Shunichi Iwanari , Hisakazu Kotani , Masanori Matsuura
发明人： Shunichi Iwanari , Hisakazu Kotani , Masanori Matsuura
IPC分类号： G06F13/00 , G06F13/28 , G11C7/00
CPC分类号： G11C16/26 , G11C7/1039 , G11C7/1051 , G11C7/1063
摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.
摘要翻译：一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

7. 发明授权

US06999349B2 Semiconductor nonvolatile storage device 有权
标题翻译：半导体非易失性存储装置
公开(公告)号：US06999349B2
公开(公告)日：2006-02-14
申请号：US10781808
申请日：2004-02-20
申请人： Kenji Misumi , Atsushi Fujiwara , Masanori Matsuura , Toshio Nishimoto
发明人： Kenji Misumi , Atsushi Fujiwara , Masanori Matsuura , Toshio Nishimoto
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/3454
摘要： A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.
摘要翻译：提供写入操作选择电路，用于选择对于存储单元晶体管元件具有规定写入时间的暂时写入操作以及用于存储单元晶体管元件的附加写入操作。提供写入时间控制电路，用于通过写入操作选择电路的输出信号来控制附加写入操作时间。

8. 发明授权

US06898490B2 Vehicle controller for controlling rewriting data in a nonvolatile memory 失效
标题翻译：用于控制在非易失性存储器中重写数据的车辆控制器
公开(公告)号：US06898490B2
公开(公告)日：2005-05-24
申请号：US10267537
申请日：2002-10-09
申请人： Tetsuya Yashiki , Masanori Matsuura
发明人： Tetsuya Yashiki , Masanori Matsuura
IPC分类号： B60R16/02 , F02D45/00 , G05B15/02 , G06F12/00 , G06F17/00 , G11C16/10 , G11C17/00 , H04L12/28 , G06F19/00
CPC分类号： G11C16/102
摘要： A vehicle controller comprises a first buffer for storing at least one data block, a second buffer for storing at least one data block, and a rewritable non-volatile memory for storing information for controlling a vehicle. The controller receives a data block from an external rewriting device to store it in the first buffer. The data block stored in the first buffer is transferred to the second buffer. The data block stored in the second buffer is written into the memory. When a first data block is written into the memory, a subsequent data block is received. Thus, the time required to rewrite data stored in the nonvolatile memory is reduced.
摘要翻译：车辆控制器包括用于存储至少一个数据块的第一缓冲器，用于存储至少一个数据块的第二缓冲器和用于存储用于控制车辆的信息的可重写非易失性存储器。控制器从外部重写装置接收数据块，将其存储在第一缓冲器中。存储在第一缓冲器中的数据块被传送到第二缓冲器。存储在第二缓冲器中的数据块被写入存储器。当第一数据块被写入存储器时，接收后续的数据块。因此，重写存储在非易失性存储器中的数据所需的时间减少。

9. 发明授权

US06480928B2 Memory rewriting system for vehicle controller 有权
标题翻译：车载控制器内存重写系统
公开(公告)号：US06480928B2
公开(公告)日：2002-11-12
申请号：US09802202
申请日：2001-03-08
申请人： Tetsuya Yashiki , Masanori Matsuura , Naohiko Mizuo
发明人： Tetsuya Yashiki , Masanori Matsuura , Naohiko Mizuo
IPC分类号： G06F1200
CPC分类号： G11C16/102 , G06F8/60
摘要： A memory rewriting system for a vehicle controller is provided. The memory rewriting system transfers a first program from a rewriting device to the vehicle to rewrite a second program stored in a memory of the vehicle controller with the first program. The first program is transferred as data blocks. Each of the data blocks includes a program code field, a first address field and a second address field. The program code field contains a partial program code of the first program. The first address field contains a leading address of the memory in which the partial program code is stored. The second address field contains a leading address of the memory in which a following partial program code transferred by another block is to be stored. The data blocks are assembled in the rewriting device. Each data block is may be a fixed length or a variable length. When the data block is transferred to the vehicle controller, a first address in the first address field of the current transferred data block is compared with a second address in the second address field of the preceding transferred data block. If the first address included in the current data block is not equal to the second address included in the preceding data block, it is determined that the current transferred data block is not correct. The vehicle controller requests the rewriting device to retransfer a correct data block that has said second address in the first address field.
摘要翻译：提供了一种用于车辆控制器的存储器重写系统。存储器重写系统将第一程序从重写装置传送到车辆，以用第一程序重写存储在车辆控制器的存储器中的第二程序。第一个程序作为数据块传送。每个数据块包括程序代码字段，第一地址字段和第二地址字段。程序代码字段包含第一程序的部分程序代码。第一个地址字段包含存储部分程序代码的存储器的前导地址。第二地址字段包含存储器的前导地址，其中存储由另一个块传送的以下部分程序代码。数据块被组装在重写装置中。每个数据块可以是固定长度或可变长度。当将数据块传送到车辆控制器时，将当前传送数据块的第一地址字段中的第一地址与先前传送数据块的第二地址字段中的第二地址进行比较。如果当前数据块中包含的第一地址不等于前面数据块中包含的第二地址，则确定当前传送的数据块不正确。车辆控制器请求重写装置在第一地址字段中重传具有所述第二地址的正确数据块。

10. 发明授权

US07248503B2 Semiconductor nonvolatile storage device 有权
标题翻译：半导体非易失性存储装置
公开(公告)号：US07248503B2
公开(公告)日：2007-07-24
申请号：US11242894
申请日：2005-10-05
申请人： Kenji Misumi , Atsushi Fujiwara , Masanori Matsuura , Toshio Nishimoto
发明人： Kenji Misumi , Atsushi Fujiwara , Masanori Matsuura , Toshio Nishimoto
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/3454
摘要： A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.
摘要翻译：提供写入操作选择电路，用于选择对于存储单元晶体管元件具有规定写入时间的暂时写入操作以及用于存储单元晶体管元件的附加写入操作。提供写入时间控制电路，用于通过写入操作选择电路的输出信号来控制附加写入操作时间。

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