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1. 发明申请

US20080028132A1 Non-volatile storage device, data storage system, and data storage method 审中-公开
标题翻译：非易失性存储设备，数据存储系统和数据存储方法
公开(公告)号：US20080028132A1
公开(公告)日：2008-01-31
申请号：US11798679
申请日：2007-05-16
申请人： Masanori Matsuura , Yasushi Gohou , Shunichi Iwanari , Yoshiaki Nakao , Hisakazu Kotani , Junichi Kato , Satoshi Mishima , Motonobu Nishimura , Toshiki Mori
发明人： Masanori Matsuura , Yasushi Gohou , Shunichi Iwanari , Yoshiaki Nakao , Hisakazu Kotani , Junichi Kato , Satoshi Mishima , Motonobu Nishimura , Toshiki Mori
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F13/1668 , G06F2212/7203 , G11C16/10
摘要： A non-volatile storage device comprises a non-volatile memory into which data is written per unit area, and a memory controller for controlling writing of data into the non-volatile memory. The memory controller comprises a first storage section for holding data input from the outside of the device, a first control section for writing data which is held by the first storage section and whose amount corresponds to the unit area, into the non-volatile memory in a unit area-by-unit area basis, and writing data which is held by the first storage section and whose amount is less than the unit area, into a second storage section, and a second control section for writing data held by the second storage section into the non-volatile memory.
摘要翻译：非易失性存储装置包括：每单位区域写入数据的非易失性存储器;以及用于控制将数据写入非易失性存储器的存储器控制器。存储器控制器包括用于保存从设备外部输入的数据的第一存储部分，用于将由第一存储部分保存并且其数量对应于单位区域的数据写入到非易失性存储器中的第一控制部分以单位面积为单位的区域，以及将由第一存储部保持的数量小于单位面积的写入数据写入到第二存储部中，以及第二控制部，用于写入由第二存储器部分进入非易失性存储器。

2. 发明授权

US07835169B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07835169B2
公开(公告)日：2010-11-16
申请号：US12368622
申请日：2009-02-10
申请人： Yasuo Murakuki , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yoshiaki Nakao
发明人： Yasuo Murakuki , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yoshiaki Nakao
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines.
摘要翻译：半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括以矩阵图案排列的多个存储单元，以及多个存储单元阵列共享的单元板板线，每个单元板线对应于存储单元的行和每个单元格板线连接到相应行之一的存储单元。每个存储单元阵列包括多个字线，每个字线对应于存储单元阵列中存储单元的行中的每一行。连接到每个单元格板行的存储单元的数量大于连接到与每个单元格板行相对应的一个字线的存储单元的数量。

3. 发明申请

US20100023840A1 ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM 审中-公开
标题翻译： ECC电路，半导体存储器件，存储器系统
公开(公告)号：US20100023840A1
公开(公告)日：2010-01-28
申请号：US12480294
申请日：2009-06-08
申请人： Yoshiaki Nakao , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yasuo Murakuki
发明人： Yoshiaki Nakao , Yasushi Gohou , Shunichi Iwanari , Masanori Matsuura , Yasuo Murakuki
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/13 , G06F11/1008 , H03M13/19
摘要： A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section.
摘要翻译：校正子产生部分从具有数据位d位和奇偶校验位k位的输入数据生成校正子。校正子表存储指示在输入数据中没有发生错误的校正子模式和指示错误位置的校正子模式。比较部分将由校正子产生部分产生的综合征与综合征表中的综合征模式进行比较，当不存在匹配该综合征的综合征模式时，输出匹配信号，并且当不存在与该综合征相匹配的症状模式时，输出不匹配信号。误差校正部分根据比较部分的匹配信号校正输入数据中的误差。

4. 发明申请

US20090210612A1 MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：内存控制器，非易失性存储器件和非易失性存储器系统
公开(公告)号：US20090210612A1
公开(公告)日：2009-08-20
申请号：US12282693
申请日：2007-03-12
申请人： Masahiro Nakanishi , Masayuki Toyama , Yutaka Nakamura , Yasushi Gohou , Masanori Matsuura , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shunichi Iwanari , Shinichi Tokumitsu
发明人： Masahiro Nakanishi , Masayuki Toyama , Yutaka Nakamura , Yasushi Gohou , Masanori Matsuura , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shunichi Iwanari , Shinichi Tokumitsu
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed.
摘要翻译：在逻辑扇区的重写处理中，传送的逻辑扇区的数据被临时存储在存储缓冲器中。当缓冲存储器已经完全填满数据时，数据被写入闪存。在包括具有大于来自外部的最小写入单位（扇区）的容量的写入单元（页）的闪存的重写处理中，可以减少撤离处理的执行次数并且可以执行快速数据重写。因此，可以使以扇区为单位重写的旧数据的撤离处理合理化，并提高数据重写速度。

5. 发明授权

US07307866B2 Ferroelectric memory and method for reading data from the ferroelectric memory 有权
标题翻译：铁电存储器和从铁电存储器读取数据的方法
公开(公告)号：US07307866B2
公开(公告)日：2007-12-11
申请号：US11132196
申请日：2005-05-19
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C11/42 , G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/22
摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.
摘要翻译：本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

6. 发明授权

US07280406B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07280406B2
公开(公告)日：2007-10-09
申请号：US11344199
申请日：2006-02-01
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

7. 发明授权

US07506099B2 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07506099B2
公开(公告)日：2009-03-17
申请号：US11519221
申请日：2006-09-12
申请人： Shunichi Iwanari , Yasushi Gohou , Yoshihisa Kato
发明人： Shunichi Iwanari , Yasushi Gohou , Yoshihisa Kato
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F2212/2022
摘要： A semiconductor storage apparatus comprising: a ferroelectric memory; an SRAM 30; a counter 41; a CAM 10 that judges whether or not a block of data requested to be read out from the ferroelectric memory is stored in the SRAM 30; a storage control unit 51 that, if a result of the judgment is negative, performs a control to read out the requested block of data from the ferroelectric memory and stores a copy of the read-out block of data into a unit storage area in the SRAM 30 that corresponds to the count value indicated by the counter 41; and a counter control unit 52 that causes the counter 41 to update the count value each time a result of the judgment is negative.
摘要翻译：一种半导体存储装置，包括：铁电存储器; 一个SRAM 30; 柜台41 判断从铁电存储器请求读出的数据块是否存储在SRAM30中的CAM10; 存储控制单元51，如果判断结果为否定，则执行控制以从强电介质存储器读出所请求的数据块，并将读出的数据块的副本存储在该单元存储区域中对应于由计数器41指示的计数值的SRAM 30; 以及计数器控制单元52，每当判断结果为负时，使计数器41更新计数值。

8. 发明申请

US20060195708A1 Memory system 有权
公开(公告)号：US20060195708A1
公开(公告)日：2006-08-31
申请号：US11338770
申请日：2006-01-25
申请人： Yoshihisa Kato , Yasushi Gohou , Masahiro Nakanishi , Masayuki Toyama , Shunichi Iwanari
发明人： Yoshihisa Kato , Yasushi Gohou , Masahiro Nakanishi , Masayuki Toyama , Shunichi Iwanari
IPC分类号： G06F1/26
CPC分类号： G06F1/3225 , G06F1/206 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： A memory system of the present invention includes a memory device having a nonvolatile memory and an access device which accesses the memory device. The memory device has a detection unit to detect a temperature of the memory device, a determination unit to determine an operating condition in accordance with the detected temperature and a notification unit to notify the access device of the determined operating condition. The access device has an interface unit to connect to the memory device and a controlling unit to control the interface unit in accordance with the notified operating condition from the memory device.

9. 发明申请

US20050265090A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20050265090A1
公开(公告)日：2005-12-01
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C7/00 , G11C29/00 , G11C29/12
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

10. 再颁专利

USRE41879E1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：USRE41879E1
公开(公告)日：2010-10-26
申请号：US12155392
申请日：2008-06-03
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

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