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    • 10. 发明申请
    • DECODER CIRCUIT
    • 解码器电路
    • US20100301902A1
    • 2010-12-02
    • US12845290
    • 2010-07-28
    • Mitsuhiro TOMOEDAMakoto MuneyasuMasahiro Hosoda
    • Mitsuhiro TOMOEDAMakoto MuneyasuMasahiro Hosoda
    • G11C8/00
    • H03K19/20G11C8/08G11C8/10G11C16/08
    • A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    • 获得正常可操作的解码器电路,而不需要解码操作的延迟,电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间,并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号,并将其反相信号作为输出信号输出。