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1. 发明授权

US06601154B2 Cache memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
公开(公告)号：US06601154B2
公开(公告)日：2003-07-29
申请号：US10084229
申请日：2002-02-28
申请人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
发明人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
IPC分类号： G06F1206
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A comparator having a hit signal that is high, before a hit check is established in each way of an address array, and that goes low, when a mishit has been established. When a clock frequency is high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check is established. When the hit check has been established, data read from a way which has the hit is output onto a data line and an operation in the way which has a mishit is stopped.

2. 发明授权

US06389523B1 Cache memory employing dynamically controlled data array start timing and a microprocessor using the same 失效
标题翻译：使用动态控制的数据阵列启动定时的高速缓存存储器和使用其的微处理器
公开(公告)号：US06389523B1
公开(公告)日：2002-05-14
申请号：US09557220
申请日：2000-04-25
申请人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
发明人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
IPC分类号： G06F1206
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.
摘要翻译：构成一个比较器，使命中信号phihit是高的，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个错误时，命中信号变低。当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。这种新颖的结构实现了高速缓存操作。当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

3. 发明授权

US5860127A Cache memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
标题翻译：使用动态控制的数据阵列启动定时的高速缓冲存储器和使用其的微型计算机
公开(公告)号：US5860127A
公开(公告)日：1999-01-12
申请号：US653278
申请日：1996-05-24
申请人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
发明人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02B60/1225
摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.
摘要翻译：构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。这种新颖的结构实现了高速缓存操作。当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

4. 发明授权

US6070234A Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
标题翻译：采用动态控制的数据阵列启动定时的Cacche存储器和使用它的微型计算机
公开(公告)号：US6070234A
公开(公告)日：2000-05-30
申请号：US118892
申请日：1998-07-20
申请人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
发明人： Yasuhisa Shimazaki , Seiichi Nagata , Katuhiro Norisue , Koichiro Ishibashi , Junichi Nishimoto , Shinichi Yoshioka , Susumu Narita
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02B60/1225
摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.
摘要翻译：构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。这种新颖的结构实现了高速缓存操作。当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

5. 发明授权

US06559006B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06559006B2
公开(公告)日：2003-05-06
申请号：US10157978
申请日：2002-05-31
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

6. 发明授权

US06436753B1 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06436753B1
公开(公告)日：2002-08-20
申请号：US09372007
申请日：1999-08-11
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218244
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth，引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

7. 发明授权

US06753231B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06753231B2
公开(公告)日：2004-06-22
申请号：US10379543
申请日：2003-03-06
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L21336
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

8. 发明授权

US07486126B2 Semiconductor integrated circuit with pulse generation sections 失效
标题翻译：具有脉冲发生部分的半导体集成电路
公开(公告)号：US07486126B2
公开(公告)日：2009-02-03
申请号：US11639141
申请日：2006-12-15
申请人： Yasuhisa Shimazaki
发明人： Yasuhisa Shimazaki
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock supply source, functional modules operated in sync with a clock signal, level sense type sequence circuits which are contained in the functional modules and configured as clock supply destinations, a clock supply system which propagates the clock signal to the level sense type sequence circuits, etc. The clock supply system includes a clock wiring which propagates the clock signal outputted from the clock generator to ends thereof via a plurality of branches. At least pulse generators are disposed in the midstream of the clock wiring. Each of the pulse generators varies timing provided to change the falling edge of the clock signal, which defines an endpoint of an input operating period of each level sense type sequence circuit.
摘要翻译：本发明提供一种用于增强操作频率并提高系统中使用至少电平检测型序列电路作为多个序列电路的可靠性的技术。微型计算机包括配置为时钟供给源的时钟发生器，与时钟信号同步操作的功能模块，功能模块中包含的并配置为时钟供给目的地的电平检测型顺序电路，传播时钟的时钟供给系统信号到电平检测类型顺序电路等。时钟供给系统包括时钟布线，其经由多个分支将从时钟发生器输出的时钟信号传播到其端部。至少脉冲发生器设置在时钟布线的中间。每个脉冲发生器改变提供的时序以改变时钟信号的下降沿，其定义每个电平检测类型顺序电路的输入操作周期的端点。

9. 发明申请

US20070182475A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20070182475A1
公开(公告)日：2007-08-09
申请号：US11639141
申请日：2006-12-15
申请人： Yasuhisa Shimazaki
发明人： Yasuhisa Shimazaki
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock supply source, functional modules operated in sync with a clock signal, level sense type sequence circuits which are contained in the functional modules and configured as clock supply destinations, a clock supply system which propagates the clock signal to the level sense type sequence circuits, etc. The clock supply system includes a clock wiring which propagates the clock signal outputted from the clock generator to ends thereof via a plurality of branches. At least pulse generators are disposed in the midstream of the clock wiring. Each of the pulse generators varies timing provided to change the falling edge of the clock signal, which defines an endpoint of an input operating period of each level sense type sequence circuit.
摘要翻译：本发明提供一种用于增强操作频率并提高系统中使用至少电平检测型序列电路作为多个序列电路的可靠性的技术。微型计算机包括配置为时钟供给源的时钟发生器，与时钟信号同步操作的功能模块，功能模块中包含的并配置为时钟供给目的地的电平检测型顺序电路，传播时钟的时钟供给系统信号到电平检测类型顺序电路等。时钟供给系统包括时钟布线，其经由多个分支将从时钟发生器输出的时钟信号传播到其端部。至少脉冲发生器设置在时钟布线的中间。每个脉冲发生器改变提供的时序以改变时钟信号的下降沿，其定义每个电平检测类型顺序电路的输入操作周期的端点。

10. 发明申请

US20060274571A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20060274571A1
公开(公告)日：2006-12-07
申请号：US11504077
申请日：2006-08-15
申请人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
发明人： Noriaki Maeda , Yoshihiro Shinozaki , Masanao Yamaoka , Yasuhisa Shimazaki , Masanori Isoda , Koji Nii
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C5/063 , G11C5/14 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

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