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1. 发明授权

US07689976B2 Compiler apparatus and linker apparatus 有权
标题翻译：编译器装置和连接器装置
公开(公告)号：US07689976B2
公开(公告)日：2010-03-30
申请号：US10950397
申请日：2004-09-28
申请人： Yasuhiro Yamamoto , Hajime Ogawa , Taketo Heishi , Shohei Michimoto
发明人： Yasuhiro Yamamoto , Hajime Ogawa , Taketo Heishi , Shohei Michimoto
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/4442
摘要： A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.
摘要翻译：提供了能够提高高速缓冲存储器的命中率的编译器，其目标是具有高速缓冲存储器的计算机，并且将源程序转换为对象程序。编译器使计算机分析用于对源程序中包含的数据对象进行分组的组信息，并根据分析结果将数据对象放入组中。编译器还使得计算机基于分组的结果生成对象程序，其中对象程序不允许属于不同组的数据对象被布置在高速缓冲存储器上具有相同设定编号的任何块中。

2. 发明申请

US20060248520A1 Program conversion device and program conversion method 审中-公开
标题翻译：程序转换装置和程序转换方法
公开(公告)号：US20060248520A1
公开(公告)日：2006-11-02
申请号：US10565530
申请日：2005-02-04
申请人： Teruo Kawabata , Hajime Ogawa , Taketo Heishi , Yasuhiro Yamamoto , Shohei Michimoto
发明人： Teruo Kawabata , Hajime Ogawa , Taketo Heishi , Yasuhiro Yamamoto , Shohei Michimoto
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler which improves the processing speed of a program execution without needlessly issuing an instruction that has a possibility of causing an interlock is targeted at a processor having an instruction that has a possibility of causing an interlock when the instruction is executed, the compiler causing a computer to function as: a loop structure transforming unit (186) which performs double looping transformation on an input program so that a loop whose iteration count is y is split off from a loop whose loop count is x and the loop whose iteration count is y is an inner loop whereas a loop whose iteration count is x/y is an outer loop; and an instruction optimum placing unit (187) which places an instruction that has a possibility of causing an interlock in the program on which the double looping transformation has been performed.
摘要翻译：一种改进程序执行的处理速度而不用不必要地发出具有引起互锁的可能性的指令的编译器针对具有在执行指令时可能引起互锁的指令的处理器，编译器引起计算机用作：循环结构变换单元（186），其对输入程序执行双循环变换，使得迭代计数为y的循环与循环计数为x的循环和迭代计数为y的循环分离是一个内循环，而迭代计数为x / y的循环是一个外循环; 以及指令最佳放置单元（187），其放置在执行了双重循环变换的程序中具有引起互锁的可能性的指令。

3. 发明授权

US07571432B2 Compiler apparatus for optimizing high-level language programs using directives 有权
标题翻译：用于使用指令优化高级语言程序的编译器设备
公开(公告)号：US07571432B2
公开(公告)日：2009-08-04
申请号：US10944831
申请日：2004-09-21
申请人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
发明人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.
摘要翻译：编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

4. 发明申请

US20050086653A1 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：US20050086653A1
公开(公告)日：2005-04-21
申请号：US10944831
申请日：2004-09-21
申请人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
发明人： Taketo Heishi , Hajime Ogawa , Yasuhiro Yamamoto , Kyoko Hattori , Shohei Michimoto , Kenji Hattori , Hirotetsu Tomita , Teruo Kawabata , Kiyoshi Nakashima
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler 58, which is a compiler that realizes program development in a fewer man hours, translates a source program 72 written in a high-level language into a machine language program. This compiler 58 is comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unit 76 that parses the source program 72; an intermediate code conversion unit 78 that converts the source program 72 into intermediate codes based on a result of the parsing performed by the parser unit 76; an optimization unit 68 that optimizes the intermediate codes according to the directive; and a code generation unit 90 that converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.
摘要翻译：编译器58是以较少的工时实现程序开发的编译器，将以高级语言编写的源程序72翻译成机器语言程序。该编译器58包括：指令获取单元，其获得应当优化要生成的机器语言程序的指令; 解析源程序72的解析器单元76; 中间代码转换单元78，其基于由解析器单元76执行的解析的结果将源程序72转换为中间代码; 优化单元68，根据该指令优化中间代码; 以及将中间代码转换为机器语言程序的代码生成单元90。上述指令是优化针对使用高速缓存的处理器的机器语言程序的指令。

5. 发明申请

US20050086651A1 Compiler apparatus and linker apparatus 有权
标题翻译：编译器装置和连接器装置
公开(公告)号：US20050086651A1
公开(公告)日：2005-04-21
申请号：US10950397
申请日：2004-09-28
申请人： Yasuhiro Yamamoto , Hajime Ogawa , Taketo Heishi , Shohei Michimoto
发明人： Yasuhiro Yamamoto , Hajime Ogawa , Taketo Heishi , Shohei Michimoto
IPC分类号： G06F12/08 , G06F9/45
CPC分类号： G06F8/4442
摘要： A compiler capable of increasing the hit rate of the cache memory is a compiler that targets at a computer having a cache memory, and that converts a source program into an object program, the compiler causing a computer to execute the following steps: a grouping step of analyzing grouping information that is used for grouping data objects included in the source program, and placing said data objects into groups based on a result of said analysis; and an object program generation step of generating the object program based on a result of the grouping performed in the grouping step, said object program not allowing data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.
摘要翻译：能够增加高速缓冲存储器的命中率的编译器是在具有高速缓存存储器的计算机上进行目标的编译器，并且将源程序转换为对象程序，编译器使计算机执行以下步骤：分组步骤分析用于对源程序中包括的数据对象进行分组的分组信息，以及基于所述分析的结果将所述数据对象分组成组; 以及目标程序生成步骤，基于在分组步骤中执行的分组的结果生成对象程序，不允许属于不同组的数据对象的任何对象程序被布置在高速缓存上具有相同设定编号的任何块中记忆。

6. 发明申请

US20080141229A1 PROCESSOR, PROGRAM CONVERSION APPARATUS, PROGRAM CONVERSION METHOD, AND COMPUTER PROGRAM 审中-公开
标题翻译：处理器，程序转换装置，程序转换方法和计算机程序
公开(公告)号：US20080141229A1
公开(公告)日：2008-06-12
申请号：US11969083
申请日：2008-01-03
申请人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
发明人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
IPC分类号： G06F9/45 , G06F9/312
CPC分类号： G06F9/30094 , G06F9/30021 , G06F9/30072
摘要： The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional new condition flag value.
摘要翻译：第一，第二和第三操作单元441至443各自根据在时钟周期的中途的时间点之前的指令执行预定的操作。当执行比较操作时，每个操作单元将结果值输出到条件标志操作单元51。条件标志操作单元51通过对（a）从条件标志寄存器46读取的值和结果值或（b）结果值本身执行逻辑运算来计算新条件标志值。条件标志操作单元51在时钟周期结束之前将新条件标志值输出到与条件指令相关的第一，第二和第三门451至453中的一个，以便控制条件新条件的无效标志值。

7. 再颁专利

USRE45199E1 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：USRE45199E1
公开(公告)日：2014-10-14
申请号：US13616573
申请日：2012-09-14
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

8. 发明授权

US07856629B2 Compiler apparatus 有权
标题翻译：编译器
公开(公告)号：US07856629B2
公开(公告)日：2010-12-21
申请号：US11420059
申请日：2006-05-24
申请人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
发明人： Shohei Michimoto , Taketo Heishi , Hajime Ogawa , Teruo Kawabata
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/433
摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.
摘要翻译：可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线中间程序，使数据依赖关系发生变化。

9. 发明授权

US07185324B2 Compiler apparatus and method for determining locations for data in memory area 有权
标题翻译：用于确定存储器区域中的数据的位置的编译器装置和方法
公开(公告)号：US07185324B2
公开(公告)日：2007-02-27
申请号：US10631960
申请日：2003-08-01
申请人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
发明人： Shohei Michimoto , Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi , Shuichi Takayama
IPC分类号： G06F9/45 , G06F12/00 , G06F12/02
CPC分类号： G06F9/5016 , G06F8/443 , G06F9/44557
摘要： Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.
摘要翻译：公开了一种编译装置，用于生成由指令集构成的指令代码，每个指令集包括指定指示存储区中的数据项的位置的m位立即值的指令。编译装置根据一个数据属性从由多个数据项组成的组X中依次选择数据项; 并且每当选择数据项时，判断所选择的数据项是否可分配给n字节存储区（n <= 2 ^{m）。当判断为否定时，编译装置根据不同的数据属性指定所有选择的数据项中的数据项，并从组X中排除指定的数据项，并重复选择，直到剩余的所有数据项在排除指定数据项之后的组X被判断为可分配给存储区。}

10. 发明授权

US08418157B2 Compiler apparatus with flexible optimization 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US08418157B2
公开(公告)日：2013-04-09
申请号：US12706329
申请日：2010-02-16
申请人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，如果转换单元和配对指令生成单元）执行来自用户的选项和编译指示的单独优化处理，遵循来自分析单元的指令等。全局区域分配单元执行优化处理，在指定要分配给全局区域的变量的最大数据大小，要分配给全局区域的变量的指定，以及关于在全局区域中未分配的变量的指定的选项和编译指示。

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