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1. 发明申请

US20110233652A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110233652A1
公开(公告)日：2011-09-29
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

2. 发明授权

US08314455B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08314455B2
公开(公告)日：2012-11-20
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

3. 发明授权

US07796439B2 Semiconductor memory device and write method thereof 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US07796439B2
公开(公告)日：2010-09-14
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C11/34 , G11C11/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

4. 发明授权

US07977733B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07977733B2
公开(公告)日：2011-07-12
申请号：US12394929
申请日：2009-02-27
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

5. 发明申请

US20110143530A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110143530A1
公开(公告)日：2011-06-16
申请号：US13033017
申请日：2011-02-23
申请人： Atsuhiro SATO , Fumitaka Arai , Yoshio Ozawa , Takeshi Kamigaichi
发明人： Atsuhiro SATO , Fumitaka Arai , Yoshio Ozawa , Takeshi Kamigaichi
IPC分类号： H01L21/3205
CPC分类号： H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/7881
摘要： A semiconductor memory device according to the present invention includes: a first transistor formed on a semiconductor substrate 11, the first transistor including a first gate-insulating film 14a that is oxynitrided; and a second transistor including a second gate-insulating film 14b formed on the semiconductor substrate 11 and a barrier film 20 formed at least partially on the second gate-insulating film 14b, the second gate-insulating film having a lower nitrogen atom concentration than the first gate-insulating film.
摘要翻译：根据本发明的半导体存储器件包括：形成在半导体衬底11上的第一晶体管，所述第一晶体管包括被氮氧化的第一栅极绝缘膜14a; 以及第二晶体管，包括形成在半导体衬底11上的第二栅极绝缘膜14b和至少部分地形成在第二栅极绝缘膜14b上的阻挡膜20，第二栅极绝缘膜具有比第一栅极绝缘膜。

6. 发明申请

US20090230450A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090230450A1
公开(公告)日：2009-09-17
申请号：US12394929
申请日：2009-02-27
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

7. 发明申请

US20080181009A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD THEREOF 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20080181009A1
公开(公告)日：2008-07-31
申请号：US12017543
申请日：2008-01-22
申请人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
发明人： Fumitaka Arai , Takeshi Kamigaichi , Atsuhiro Sato
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642
摘要： A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.
摘要翻译：半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入细胞再次。

8. 发明授权

US08044448B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08044448B2
公开(公告)日：2011-10-25
申请号：US12508904
申请日：2009-07-24
申请人： Takeshi Kamigaichi , Fumitaka Arai
发明人： Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/1203
摘要： A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.
摘要翻译：非易失性半导体存储器件包括：具有串联连接的存储单元的存储单元阵列区域; 设置在所述存储单元阵列区域下方的控制电路区域; 以及电连接控制电路区域和存储单元阵列区域的互连部分。存储单元阵列区域包括：具有存储单元的多个第一存储单元区域; 和多个连接区域。互连部分设置在连接区域中。第一存储单元区域在与存储单元阵列区域和控制电路区域的层叠方向正交的第一方向上以第一间距设置。连接区域设置在与第一方向相互相邻的第一存储单元区域和与层叠方向和第一方向正交的第二方向上的第二间距处。

9. 发明申请

US20100020608A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100020608A1
公开(公告)日：2010-01-28
申请号：US12508904
申请日：2009-07-24
申请人： Takeshi KAMIGAICHI , Fumitaka Arai
发明人： Takeshi KAMIGAICHI , Fumitaka Arai
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/1203
摘要： A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.
摘要翻译：非易失性半导体存储器件包括：具有串联连接的存储单元的存储单元阵列区域; 设置在所述存储单元阵列区域下方的控制电路区域; 以及电连接控制电路区域和存储单元阵列区域的互连部分。存储单元阵列区域包括：具有存储单元的多个第一存储单元区域; 和多个连接区域。互连部分设置在连接区域中。第一存储单元区域在与存储单元阵列区域和控制电路区域的层叠方向正交的第一方向上以第一间距设置。连接区域设置在与第一方向相互相邻的第一存储单元区域和与层叠方向和第一方向正交的第二方向上的第二间距处。

10. 发明申请

US20070224736A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD THEREFOR 审中-公开
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20070224736A1
公开(公告)日：2007-09-27
申请号：US11756300
申请日：2007-05-31
申请人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L21/8239
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： A fabrication method for a nonvolatile semiconductor memory forming gate insulating films for a memory cell transistor and a select gate transistor on a semiconductor substrate, forming a floating gate for the memory cell transistor and a gate electrode for the select gate transistor, forming a cap insulating film for the floating gate, forming a device isolating region, depositing an inter-gate insulating film between the floating gate and control gates for the memory cell transistor, forming a control gate for the memory cell transistor and a gate interconnect for the select gate transistor, forming a salicide control insulating film across the entire surface of the device, and selectively removing the salicide control insulating film on the control gate and on an exposed surface of the semiconductor substrate.
摘要翻译：一种在半导体衬底上形成用于存储单元晶体管和选择栅极晶体管的栅极绝缘膜的非易失性半导体存储器的制造方法，形成用于存储单元晶体管的浮动栅极和用于选择栅极晶体管的栅电极，形成绝缘帽形成器件隔离区域，在浮置栅极和存储单元晶体管的控制栅极之间沉积栅极间绝缘膜，形成用于存储单元晶体管的控制栅极和用于选择栅极晶体管的栅极互连在整个装置的表面上形成一个自对准硅化物控制绝缘膜，并选择性地去除控制栅极上和该半导体衬底的暴露表面上的自对准硅化物控制绝缘膜。

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