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1. 发明授权

US06486518B1 Structures and method with bitline self-aligned to vertical connection 有权
标题翻译：具有位线自对准到垂直连接的结构和方法
公开(公告)号：US06486518B1
公开(公告)日：2002-11-26
申请号：US09407420
申请日：1999-09-29
申请人： Yasuhiro Okumoto , Michio Nishimura , Toshiyuki Nagata
发明人： Yasuhiro Okumoto , Michio Nishimura , Toshiyuki Nagata
IPC分类号： H01L27108
CPC分类号： H01L27/10814 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.
摘要翻译：将金属位线与位线上的电容器垂直互连的方法。在这类实施例中，垂直互连支柱是在完成位线的制造之前形成的。为了实现这一点，使用允许其沿着垂直互连柱的壁垂直延伸但不在位线金属和垂直互连柱之间形成任何电连接的台阶来对位线金属进行图案化。

2. 发明授权

US06407423B1 Staggered-edge capacitor electrode 有权
公开(公告)号：US06407423B1
公开(公告)日：2002-06-18
申请号：US09909973
申请日：2001-07-23
申请人： Yasuhiro Okumoto
发明人： Yasuhiro Okumoto
IPC分类号： H01G27108
CPC分类号： H01L28/88
摘要： A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.

3. 发明申请

US20070004051A1 Processing method and device 审中-公开
标题翻译：处理方法和装置
公开(公告)号：US20070004051A1
公开(公告)日：2007-01-04
申请号：US10539246
申请日：2003-12-17
申请人： Yasuhiro Okumoto , Wataru Karasawa
发明人： Yasuhiro Okumoto , Wataru Karasawa
IPC分类号： H01L21/00
CPC分类号： H01L21/67271 , G05B19/41875 , G05B2219/32209 , H01J37/32935 , H01L21/67253 , Y02P90/22
摘要： A processing system has a processing section for continuously processing a member to be processed; an inspection section for inspecting a processed state of the member processed by the processing section; a processed state determination section for determining whether the processed state is defective/nondefective, on the basis of a result of inspection performed by the inspection section; a continuity determination section for determining whether or not a defective determination is continuously made when the processed state is determined to be defective by the processed state determination section; and a processing control section for controlling processing so as to stop processing of the member continuously performed by the processing section when the continuity determination section determines that the defective determination is continuously made.
摘要翻译：处理系统具有用于连续处理要处理的部件的处理部分; 检查部，检查由处理部处理的部件的处理状态; 处理状态判定部，其根据检查部的检查结果，判断处理状态是否有缺陷/无效; 连续性确定部分，用于当处理状态确定部分确定处理状态有缺陷时，确定是否连续地进行故障判定; 以及处理控制部分，用于当连续性确定部分确定连续进行了缺陷判定时，控制处理以停止处理部件连续执行的部件的处理。

4. 发明授权

US06645824B1 Combined optical profilometry and projection microscopy of integrated circuit structures 有权
标题翻译：集成电路结构的组合光学轮廓测量和投影显微镜
公开(公告)号：US06645824B1
公开(公告)日：2003-11-11
申请号：US10137200
申请日：2002-04-30
申请人： Wenge Yang , Junwei Bao , Xinhui Niu , Nickhil Jakatdar , Yasuhiro Okumoto
发明人： Wenge Yang , Junwei Bao , Xinhui Niu , Nickhil Jakatdar , Yasuhiro Okumoto
IPC分类号： H01L2176
CPC分类号： G01N21/4788 , Y10S977/869 , Y10S977/881
摘要： A metrology method and system of structures on a wafer includes obtaining a projection image of at least a first portion of the structures on the wafer using a first metrology apparatus. A profile of at least a second portion of the structure on the wafer is obtained using a second metrology apparatus. The information from the profile obtained using the second metrology apparatus and the information from the projection image obtained using the first metrology apparatus are combined using a processor.
摘要翻译：晶片上的测量方法和结构系统包括使用第一测量装置获得晶片上至少第一部分结构的投影图像。使用第二测量装置获得晶片上的结构的至少第二部分的轮廓。使用第二测量装置获得的轮廓的信息和使用第一测量装置获得的投影图像的信息使用处理器进行组合。

5. 发明授权

US06373092B1 Staggered-edge capacitor electrode 有权
标题翻译：交错电容电极
公开(公告)号：US06373092B1
公开(公告)日：2002-04-16
申请号：US09405270
申请日：1999-09-23
申请人： Yasuhiro Okumoto
发明人： Yasuhiro Okumoto
IPC分类号： H01L3300
CPC分类号： H01L28/88
摘要： A capacitor electrode and method of making having increased surface area because of the presence of pits in the side walls of the electrode thus increasing the capacitance of the capacitor while still maintaining the packing density of the integrated circuit.
摘要翻译：电容器电极和制造方法由于在电极的侧壁中存在凹坑而具有增加的表面积，从而在仍然保持集成电路的堆积密度的同时增加电容器的电容。

6. 发明授权

US5629225A Method of making a cylindrical electrode 失效
标题翻译：制作圆柱形电极的方法
公开(公告)号：US5629225A
公开(公告)日：1997-05-13
申请号：US478635
申请日：1995-06-07
申请人： Takashi Iwakiri , Kiyomi Hirose , Hiroto Shinozuka , Osaomi Enomoto , Yasuhiro Okumoto
发明人： Takashi Iwakiri , Kiyomi Hirose , Hiroto Shinozuka , Osaomi Enomoto , Yasuhiro Okumoto
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60 , H01L28/91
摘要： A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.
摘要翻译：一种用于包含屏幕型结构的圆柱形堆叠单元电容器的动态RAM的制造方法。 SiO 2层22形成在多晶硅层11（或半导体衬底1）上，用作预成型件或间隔件。氮化物层31层叠在该SiO 2层上，氮化物层31和SiO 2层22被加工成几乎相同的图案。然后，使用氮化物层31作为掩模来蚀刻SiO 2层22的外表面，使得氮化物层31在通过蚀刻去除的区域中形成横向突起结构31A。多晶硅层23从包括该突出部分的氮化物层31和SiO 2层22的顶部附着到用作电容器下电极的硅层11的顶部。蚀刻多晶硅层23，以在氮化物层31的突出部分31A正下方的SiO 2层22的外表面上留下多晶硅层23的一部分。

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