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1. 发明授权

US08557668B2 Method for forming N-shaped bottom stress liner 有权
标题翻译：形成N型底应力衬垫的方法
公开(公告)号：US08557668B2
公开(公告)日：2013-10-15
申请号：US13348771
申请日：2012-01-12
申请人： Xiaodong Yang , Yanxiang Liu , Vara Govindeswara Reddy Vakada , Jinping Liu , Min Dai
发明人： Xiaodong Yang , Yanxiang Liu , Vara Govindeswara Reddy Vakada , Jinping Liu , Min Dai
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/6656 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849 , H01L29/78654 , H01L29/78696
摘要： Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
摘要翻译：形成具有n形底部应力衬垫的半导体器件。实施例包括在衬底上形成突起，在突起上保形地形成牺牲材料层，在硅层上的牺牲材料层上方形成栅极堆叠，去除牺牲材料层以形成隧道，并在其中形成应力衬垫隧道符合突起的形状。实施例还包括在形成应力衬垫之前在牺牲材料层上形成硅层并且在钝化层之前衬套隧道。

2. 发明申请

US20130049142A1 TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE 有权
标题翻译：具有降低PARASIIC电容的晶体管
公开(公告)号：US20130049142A1
公开(公告)日：2013-02-28
申请号：US13218988
申请日：2011-08-26
申请人： Yanxiang Liu , Jinping Liu , Min Dai , Xiaodong Yang
发明人： Yanxiang Liu , Jinping Liu , Min Dai , Xiaodong Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6653 , H01L29/4966 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66628
摘要： Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.
摘要翻译：具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。实施例包括晶体管，其包括与替代金属栅电极间隔开的沟槽硅化物层，以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构，去除可移除栅极，在氮化物间隔物上形成高k材料层，在高k材料上形成金属氮化物层，填充开口用绝缘材料，然后去除其一部分以形成凹槽，去除金属氮化物层和高k材料层，沉积SiO 2或低k材料层，并在剩余的凹槽中形成替换金属栅极。

3. 发明申请

US20130005103A1 METHODS FOR FABRICATING A FINFET INTEGRATED CIRCUIT ON A BULK SILICON SUBSTRATE 有权
标题翻译：用于制造大量硅基板上的FINFET集成电路的方法
公开(公告)号：US20130005103A1
公开(公告)日：2013-01-03
申请号：US13172635
申请日：2011-06-29
申请人： Yanxiang Liu , Xiaodong Yang , Jinping Liu
发明人： Yanxiang Liu , Xiaodong Yang , Jinping Liu
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/3065 , H01L29/66795 , H01L29/785
摘要： Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.
摘要翻译：提供了用于制造FINFET集成电路的方法，其包括外延生长第一硅锗层和覆盖硅衬底的第二硅层。使用第一硅锗层作为蚀刻停止层，蚀刻第二硅层以形成硅翅片。除去翅片下面的第一硅锗层以形成鳍片下面的空隙，并且用绝缘材料填充空隙。然后形成覆盖鳍片的栅极结构。

4. 发明授权

US08637372B2 Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate 有权
标题翻译：在体硅衬底上制造FINFET集成电路的方法
公开(公告)号：US08637372B2
公开(公告)日：2014-01-28
申请号：US13172635
申请日：2011-06-29
申请人： Yanxiang Liu , Xiaodong Yang , Jinping Liu
发明人： Yanxiang Liu , Xiaodong Yang , Jinping Liu
IPC分类号： H01L21/336
CPC分类号： H01L21/3065 , H01L29/66795 , H01L29/785
摘要： Methods are provided for fabricating a FINFET integrated circuit that includes epitaxially growing a first silicon germanium layer and a second silicon layer overlying a silicon substrate. The second silicon layer is etched to form a silicon fin using the first silicon germanium layer as an etch stop. The first silicon germanium layer underlying the fin is removed to form a void underlying the fin and the void is filled with an insulating material. A gate structure is then formed overlying the fin.
摘要翻译：提供了用于制造FINFET集成电路的方法，其包括外延生长覆盖硅衬底的第一硅锗层和第二硅层。使用第一硅锗层作为蚀刻停止层，蚀刻第二硅层以形成硅翅片。除去翅片下面的第一硅锗层以形成鳍片下面的空隙，并且用绝缘材料填充空隙。然后形成覆盖鳍片的栅极结构。

5. 发明申请

US20130181260A1 METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER 有权
标题翻译：形成N型衬底应力衬里的方法
公开(公告)号：US20130181260A1
公开(公告)日：2013-07-18
申请号：US13348771
申请日：2012-01-12
申请人： Xiaodong Yang , Yanxiang Liu , Vara Govindeswara Reddy Vakada , Jinping Liu , Min Dai
发明人： Xiaodong Yang , Yanxiang Liu , Vara Govindeswara Reddy Vakada , Jinping Liu , Min Dai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/6656 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849 , H01L29/78654 , H01L29/78696
摘要： Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
摘要翻译：形成具有n形底部应力衬垫的半导体器件。实施例包括在衬底上形成突起，在突起上保形地形成牺牲材料层，在硅层上的牺牲材料层上方形成栅极堆叠，去除牺牲材料层以形成隧道，并在其中形成应力衬垫隧道符合突起的形状。实施例还包括在形成应力衬垫之前在牺牲材料层上形成硅层并且在钝化层之前衬套隧道。

6. 发明授权

US08809962B2 Transistor with reduced parasitic capacitance 有权
标题翻译：降低寄生电容的晶体管
公开(公告)号：US08809962B2
公开(公告)日：2014-08-19
申请号：US13218988
申请日：2011-08-26
申请人： Yanxiang Liu , Jinping Liu , Min Dai , Xiaodong Yang
发明人： Yanxiang Liu , Jinping Liu , Min Dai , Xiaodong Yang
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/49 , H01L29/51
CPC分类号： H01L29/6653 , H01L29/4966 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66628
摘要： Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.
摘要翻译：具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。实施例包括晶体管，其包括与替代金属栅电极间隔开的沟槽硅化物层，以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构，去除可移除栅极，在氮化物间隔物上形成高k材料层，在高k材料上形成金属氮化物层，填充开口用绝缘材料，然后去除其一部分以形成凹槽，去除金属氮化物层和高k材料层，沉积SiO 2或低k材料层，并在剩余的凹槽中形成替换金属栅极。

7. 发明授权

US08809178B2 Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents 有权
标题翻译：用替换栅极形成大量FinFET器件的方法，以减少冲击穿过漏电流
公开(公告)号：US08809178B2
公开(公告)日：2014-08-19
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

8. 发明申请

US20130032890A1 SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES 有权
标题翻译：自适应CMOS器件的上拉电阻
公开(公告)号：US20130032890A1
公开(公告)日：2013-02-07
申请号：US13197631
申请日：2011-08-03
申请人： Yanxiang Liu , Xiaodong Yang , Gan Wang
发明人： Yanxiang Liu , Xiaodong Yang , Gan Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0921
摘要： CMOS devices (60, 61, 61′) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62′, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61′) are less likely to go into latch-up with increasing operating temperature.
摘要翻译：具有改进的闭锁稳健性的CMOS器件（60,61,61'）通过包括源极 - 漏极（24,25; 31,32）下面的一个或两个WELL区域（22,29）和主体触点掺杂与相应的WELL区相同导电类型的深受体或深供体（或两者）的一个或多个另外的区域（62,62'，62-2），并且其电离随着工作温度的升高而显着增加。这些其他区域的电导率的增加是由于深受体或供体离子的电离增加导致的，全部或部分，先前的固有的寄生NPN和/或PNP双极晶体管的增益的温度驱动增加的结果艺术CMOS结构。通过钳位或降低寄生双极晶体管的增益，CMOS器件（60,61,61'）不太可能随着工作温度的升高而进入闭锁状态。

9. 发明授权

US08841732B2 Self-adjusting latch-up resistance for CMOS devices 有权
标题翻译： CMOS器件的自调节闭锁电阻
公开(公告)号：US08841732B2
公开(公告)日：2014-09-23
申请号：US13197631
申请日：2011-08-03
申请人： Yanxiang Liu , Xiaodong Yang , Gan Wang
发明人： Yanxiang Liu , Xiaodong Yang , Gan Wang
IPC分类号： H01L27/092
CPC分类号： H01L27/0921
摘要： CMOS devices (60, 61, 61′) having improved latch-up robustness are provided by including with one or both WELL regions (22, 29) underlying the source-drains (24, 25; 31, 32) and the body contacts (27, 34), one or more further regions (62, 62′, 62-2) doped with deep acceptors or deep donors (or both) of the same conductivity type as the corresponding WELL region and whose ionization substantially increases as operating temperature increases. The increase in conductivity exhibited by these further regions as a result of the increasing ionization of the deep acceptors or donors off-sets, in whole or part, the temperature driven increase in gain of the parasitic NPN and/or PNP bipolar transistors inherent in prior art CMOS structures. By clamping or lowering the gain of the parasitic bipolar transistors, the CMOS devices (60, 61, 61′) are less likely to go into latch-up with increasing operating temperature.
摘要翻译：具有改进的闭锁稳健性的CMOS器件（60,61,61'）通过包括源极 - 漏极（24,25; 31,32）下面的一个或两个WELL区域（22,29）和主体触点掺杂与相应的WELL区相同导电类型的深受体或深供体（或两者）的一个或多个另外的区域（62,62'，62-2），并且其电离随着工作温度的升高而显着增加。这些其他区域的电导率的增加是由于深受体或供体的电离离子的增加，全部或部分地升高了先前的固有的寄生NPN和/或PNP双极晶体管的增益的温度驱动增加的结果艺术CMOS结构。通过钳位或降低寄生双极晶体管的增益，CMOS器件（60,61,61'）不太可能随着工作温度的升高而进入闭锁状态。

10. 发明申请

US20130224945A1 METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS 有权
标题翻译：形成具有更换盖的块状FINFET器件的方法，以减少通过泄漏电流的冲击
公开(公告)号：US20130224945A1
公开(公告)日：2013-08-29
申请号：US13408139
申请日：2012-02-29
申请人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
发明人： Yanxiang Liu , Michael Hargrove , Xiaodong Yang , Hans Van Meer , Laegu Kang , Christian Gruensfelder , Srikanth Samavedam
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L29/66795
摘要： One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷，以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

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