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1. 发明申请

US20140071144A1 METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM 有权
标题翻译：在异位平台上配置共享点的方法和装置
公开(公告)号：US20140071144A1
公开(公告)日：2014-03-13
申请号：US14020616
申请日：2013-09-06
申请人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
IPC分类号： G06T1/60
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译：一种促进异构平台中的共享指针的方法和装置。在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的处理核心。异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。

2. 发明授权

US08566537B2 Method and apparatus to facilitate shared pointers in a heterogeneous platform 有权
标题翻译：促进异构平台中共享指针的方法和装置
公开(公告)号：US08566537B2
公开(公告)日：2013-10-22
申请号：US13074779
申请日：2011-03-29
申请人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译：一种促进异构平台中的共享指针的方法和装置。在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的处理核心。异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。

3. 发明授权

US08949777B2 Methods and systems for mapping a function pointer to the device code 有权
标题翻译：将功能指针映射到设备代码的方法和系统
公开(公告)号：US08949777B2
公开(公告)日：2015-02-03
申请号：US13092500
申请日：2011-04-22
申请人： Yang Ni , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman
发明人： Yang Ni , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/52
摘要： Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device.
摘要翻译：介绍了将功能指针映射到设备代码的方法。在一个实施例中，一种方法包括识别可由处理设备执行的功能。该方法包括生成代码，其包括对应于第一处理设备的第一代码，第二代码对应于第二处理设备。第二处理装置在结构上与第一处理装置不同。该方法还包括将第二代码存储在字节串中，使得如果功能将被第二处理设备执行，则可检索第二代码。

4. 发明申请

US20120272210A1 METHODS AND SYSTEMS FOR MAPPING A FUNCTION POINTER TO THE DEVICE CODE 有权
标题翻译：将功能指针映射到设备代码的方法和系统
公开(公告)号：US20120272210A1
公开(公告)日：2012-10-25
申请号：US13092500
申请日：2011-04-22
申请人： Yang Ni , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman
发明人： Yang Ni , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/52
摘要： Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device.
摘要翻译：介绍了将功能指针映射到设备代码的方法。在一个实施例中，一种方法包括识别可由处理设备执行的功能。该方法包括生成代码，其包括对应于第一处理设备的第一代码，第二代码对应于第二处理设备。第二处理装置在结构上与第一处理装置不同。该方法还包括将第二代码存储在字节串中，使得如果功能将被第二处理设备执行，则可检索第二代码。

5. 发明授权

US09069670B2 Mechanisms to accelerate transactions using buffered stores 有权
公开(公告)号：US09069670B2
公开(公告)日：2015-06-30
申请号：US13658212
申请日：2012-10-23
申请人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
IPC分类号： G06F12/08 , G06F9/46 , G06F12/10 , G06F9/52 , G06F9/30
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/1027 , G06F2212/621
摘要： In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

6. 发明申请

US20130046947A1 Mechanisms To Accelerate Transactions Using Buffered Stores 有权
公开(公告)号：US20130046947A1
公开(公告)日：2013-02-21
申请号：US13658360
申请日：2012-10-23
申请人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
IPC分类号： G06F12/16
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/1027 , G06F2212/621
摘要： In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

7. 发明授权

US08316194B2 Mechanisms to accelerate transactions using buffered stores 有权
标题翻译：使用缓冲存储加速事务的机制
公开(公告)号：US08316194B2
公开(公告)日：2012-11-20
申请号：US12638054
申请日：2009-12-15
申请人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
IPC分类号： G06F12/00 , G06F12/08 , G06F12/16
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/1027 , G06F2212/621
摘要： In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。描述和要求保护其他实施例。

8. 发明申请

US20110145512A1 Mechanisms To Accelerate Transactions Using Buffered Stores 有权
标题翻译：使用缓冲商店加速交易的机制
公开(公告)号：US20110145512A1
公开(公告)日：2011-06-16
申请号：US12638054
申请日：2009-12-15
申请人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Yang Ni , Bratin Saha , Vadim Bassin , Gad Sheaffer , David Callahan , Jan Gray
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/1027 , G06F2212/621
摘要： In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。描述和要求保护其他实施例。

9. 发明授权

US08555016B2 Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system 有权
公开(公告)号：US08555016B2
公开(公告)日：2013-10-08
申请号：US12337507
申请日：2008-12-17
申请人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
发明人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
IPC分类号： G06F12/00
CPC分类号： G06F9/467 , G06F9/528 , G06F17/30351 , G06F17/30353 , G06F17/30356 , G06F17/30359
摘要： A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

10. 发明申请

US20120159495A1 NON-BLOCKING WAIT-FREE DATA-PARALLEL SCHEDULER 有权
标题翻译：非阻塞等待数据并行调度器
公开(公告)号：US20120159495A1
公开(公告)日：2012-06-21
申请号：US12971891
申请日：2010-12-17
申请人： Mohan Rajagopalan , Ali-Reza Adl-Tabatabai , Yang Ni , Adam Welc , Richard L. Hudson
发明人： Mohan Rajagopalan , Ali-Reza Adl-Tabatabai , Yang Ni , Adam Welc , Richard L. Hudson
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/5066
摘要： Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.
摘要翻译：描述了用于将数据并行任务调度到处理系统的多个线程执行单元上的方法，系统和介质。描述无锁队列结构和操作方法的实施例以实现用于调度细粒度数据并行任务以在计算系统中执行的方法。多个工作线程之一的工作相对于其他工作线程是等待的。队列的每个节点都保存对可以由多个线程执行单元同时执行的任务的引用，但每个节点都在不同的数据子集上。各种实施例涉及在不在硬件中执行这样的调度的多线程计算平台上的数据并行任务的基于软件的调度。还描述和要求保护其他实施例。

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