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    • 1. 发明授权
    • Data management in solid state storage devices
    • 固态存储设备中的数据管理
    • US09176817B2
    • 2015-11-03
    • US13617571
    • 2012-09-14
    • Roy D. CideciyanEvangelos S. EleftheriouRobert HaasXiao-Yu HuIlias Iliadis
    • Roy D. CideciyanEvangelos S. EleftheriouRobert HaasXiao-Yu HuIlias Iliadis
    • G11C29/00G06F11/10H03M13/05
    • G06F11/108G06F11/1008G06F11/1068H03M13/05
    • A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the group containing write locations in that block. The recovered data is then re-stored as new input data.
    • 提供一种用于控制固态存储装置的机构,其中固态存储器包括每个包括多个数据写入位置的可擦除块。 输入数据被存储在连续的数据写入位置组中,每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。 输入数据被纠错编码,使得每个组包含用于该组中的输入数据的纠错码。 指示固态存储器中的输入数据的位置的元数据被保存在存储器中。 还保持了存储在每个数据写入位置中的数据的有效性的指示。 在擦除块之前,从包含该块中的写入位置的组中恢复有效的输入数据。 然后将恢复的数据重新存储为新的输入数据。
    • 4. 发明申请
    • Data Management in Solid State Storage Devices
    • 固态存储设备中的数据管理
    • US20120266050A1
    • 2012-10-18
    • US13516053
    • 2010-12-16
    • Roy D. CideciyanEvangelos S. EleftheriouRobert HaasXiao-Yu Hullias Iliadis
    • Roy D. CideciyanEvangelos S. EleftheriouRobert HaasXiao-Yu Hullias Iliadis
    • H03M13/05G06F11/10
    • G06F11/108G06F11/1008G06F11/1068H03M13/05
    • A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory, An indication of validity of data stored in each data write location is also maintained, Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data.
    • 提供了一种用于控制固态存储装置的机构,其中固态存储器包括每个包括多个数据写入位置的可擦除块。 输入数据被存储在连续的数据写入位置组中,每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。 输入数据被纠错编码,使得每个组包含用于该组中的输入数据的纠错码。 指示固态存储器中的输入数据的位置的元数据被保持在存储器中,还保持存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前,有效的输入数据从该或每个 该组在该块中包含写入位置。 然后将恢复的数据重新存储为新的输入数据。
    • 5. 发明授权
    • Decoding of LDPC code
    • LDPC码的解码
    • US09531406B2
    • 2016-12-27
    • US14358609
    • 2011-05-25
    • Evangelos S. EleftheriouRobert HaasXiao-Yu HuDung Nguyen
    • Evangelos S. EleftheriouRobert HaasXiao-Yu HuDung Nguyen
    • H03M13/11H03M13/29
    • H03M13/1105H03M13/1108H03M13/2957
    • It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
    • 提供了一种用于解码由LPDC码编码的比特序列的方法。 该方法包括提供一组位状态,包括第一状态和第二状态,以及一组条件以改变包括第一条件5和第二状态的位状态。 第一个条件和第二个条件是不同的。 该方法包括读取序列的每个比特的值,根据读取的值将每个比特与组的相应状态相关联,确定满足评估条件并改变目标比特的状态作为结果 条件得到满足 然后,该方法可以根据其状态设置10序列的目标比特的值。 这种方法提供了一种解码方案,用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列,只有稍微增加的复杂度。
    • 6. 发明授权
    • Data management in solid state storage devices
    • 固态存储设备中的数据管理
    • US08904261B2
    • 2014-12-02
    • US13516053
    • 2010-12-16
    • Roy D. CideciyanEvangelos S. EleftheriouRobert HaasXiao-Yu HuIlias Iliadis
    • Roy D. CideciyanEvangelos S. EleftheriouRobert HaasXiao-Yu HuIlias Iliadis
    • G11C29/00H03M13/05G06F11/10
    • G06F11/108G06F11/1008G06F11/1068H03M13/05
    • A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the each said group containing write locations in that block. The recovered data is then re-stored as new input data.
    • 提供了一种用于控制固态存储装置的机构,其中固态存储器包括每个包括多个数据写入位置的可擦除块。 输入数据被存储在连续的数据写入位置组中,每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。 输入数据被纠错编码,使得每个组包含用于该组中的输入数据的纠错码。 指示固态存储器中的输入数据的位置的元数据被保存在存储器中。 还保持了存储在每个数据写入位置中的数据的有效性的指示。 在擦除块之前,从包含该块中的写入位置的每个所述组恢复有效的输入数据。 然后将恢复的数据重新存储为新的输入数据。
    • 9. 发明申请
    • FLASH MEMORY CONTROLLER
    • 闪存控制器
    • US20120278544A1
    • 2012-11-01
    • US13515118
    • 2010-12-09
    • Evangelos S. EleftheriouRobert HaasXiao-Yu Hu
    • Evangelos S. EleftheriouRobert HaasXiao-Yu Hu
    • G06F12/02
    • G06F13/1668G06F9/3004G11C7/1042
    • A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.
    • 闪存控制器通过第一闪存存储器接口耦合到第一闪存存储器封装,并通过第一闪存存储器接口耦合到第二闪存存储器封装。 闪存控制器被设计为接收与第一闪存存储器包相关的第一指令,并且根据第一指令执行第一处理。 闪存控制器还被设计为接收与第二闪存存储器包相关的第二指令,并且根据第二指令执行第二处理。 闪存控制器还适用于将第一进程分成至少两个第一子步骤,并将第二进程分成至少两个第二子步骤。 闪存控制器还适用于执行第一和第二子步骤,并且用于交错执行第一和第二子步骤。