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1. 发明申请

US20150052413A1 DECODING OF LDPC CODE 有权
标题翻译： LDPC码的解码
公开(公告)号：US20150052413A1
公开(公告)日：2015-02-19
申请号：US14358609
申请日：2011-05-25
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
IPC分类号： H03M13/11
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

2. 发明授权

US09531406B2 Decoding of LDPC code 有权
标题翻译： LDPC码的解码
公开(公告)号：US09531406B2
公开(公告)日：2016-12-27
申请号：US14358609
申请日：2011-05-25
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
IPC分类号： H03M13/11 , H03M13/29
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

3. 发明授权

US09176817B2 Data management in solid state storage devices 有权
标题翻译：固态存储设备中的数据管理
公开(公告)号：US09176817B2
公开(公告)日：2015-11-03
申请号：US13617571
申请日：2012-09-14
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G11C29/00 , G06F11/10 , H03M13/05
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1068 , H03M13/05
摘要： A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the group containing write locations in that block. The recovered data is then re-stored as new input data.
摘要翻译：提供一种用于控制固态存储装置的机构，其中固态存储器包括每个包括多个数据写入位置的可擦除块。输入数据被存储在连续的数据写入位置组中，每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。指示固态存储器中的输入数据的位置的元数据被保存在存储器中。还保持了存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，从包含该块中的写入位置的组中恢复有效的输入数据。然后将恢复的数据重新存储为新的输入数据。

4. 发明授权

US08688914B2 Promotion of partial data segments in flash cache 有权
标题翻译：在Flash缓存中促进部分数据段
公开(公告)号：US08688914B2
公开(公告)日：2014-04-01
申请号：US13286465
申请日：2011-11-01
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Karl A. Nielsen , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Karl A. Nielsen , Roman A. Pletka
IPC分类号： G06F12/00
CPC分类号： G06F3/0619 , G06F3/0646 , G06F3/0688 , G06F12/0246 , G06F12/0253 , G06F12/0811 , G06F12/0862 , G06F12/0864 , G06F12/0871 , G06F12/0897 , G06F12/122 , G06F12/127 , G06F12/128 , G06F2212/1016 , G06F2212/154 , G06F2212/222 , G06F2212/283 , G06F2212/604 , G06F2212/702 , G06F2212/7201
摘要： For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage.
摘要翻译：为了以更有效的方式有效地在二级存储器中运行轨迹，对于与用于控制主存储器中的轨道的定时的顺序位一起使用的时间位，时间位和顺序位从主存储器传送到辅助存储器。时间位允许在辅助存储器上老化。

5. 发明授权

US08688913B2 Management of partial data segments in dual cache systems 有权
标题翻译：双缓存系统中部分数据段的管理
公开(公告)号：US08688913B2
公开(公告)日：2014-04-01
申请号：US13286454
申请日：2011-11-01
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Matthew J. Kalos , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0868 , G06F12/0891 , G06F12/0897 , G06F12/126 , G06F2212/1021 , G06F2212/1041 , G06F2212/222 , G06F2212/283
摘要： For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache. Unrequested data of the whole data segment is split and positioned at a Least Recently Used (LRU) portion of the demotion queue of the higher level of cache. The unrequested data is pinned in place until a write of the whole data segment to the lower level of cache completes.
摘要翻译：为了在由处理器具有较低和较高级别的高速缓存的计算存储环境中移动部分数据段，将包含部分数据段中的一个的整个数据段升级到较低级别和更高级别的高速缓存。整个数据段的请求数据被分割并定位在较高级缓存的降级队列的最近使用（MRU）部分。整个数据段的未请求的数据被分割并定位在较高级别的缓存的降级队列的最近最少使用（LRU）部分。未请求的数据被固定到位，直到整个数据段写入缓存的较低级别完成。

6. 发明申请

US20120266050A1 Data Management in Solid State Storage Devices 有权
标题翻译：固态存储设备中的数据管理
公开(公告)号：US20120266050A1
公开(公告)日：2012-10-18
申请号：US13516053
申请日：2010-12-16
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , llias Iliadis
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , llias Iliadis
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1068 , H03M13/05
摘要： A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory, An indication of validity of data stored in each data write location is also maintained, Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data.
摘要翻译：提供了一种用于控制固态存储装置的机构，其中固态存储器包括每个包括多个数据写入位置的可擦除块。输入数据被存储在连续的数据写入位置组中，每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。指示固态存储器中的输入数据的位置的元数据被保持在存储器中，还保持存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，有效的输入数据从该或每个该组在该块中包含写入位置。然后将恢复的数据重新存储为新的输入数据。

7. 发明授权

US08904261B2 Data management in solid state storage devices 有权
标题翻译：固态存储设备中的数据管理
公开(公告)号：US08904261B2
公开(公告)日：2014-12-02
申请号：US13516053
申请日：2010-12-16
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G11C29/00 , H03M13/05 , G06F11/10
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1068 , H03M13/05
摘要： A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the each said group containing write locations in that block. The recovered data is then re-stored as new input data.
摘要翻译：提供了一种用于控制固态存储装置的机构，其中固态存储器包括每个包括多个数据写入位置的可擦除块。输入数据被存储在连续的数据写入位置组中，每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。指示固态存储器中的输入数据的位置的元数据被保存在存储器中。还保持了存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，从包含该块中的写入位置的每个所述组恢复有效的输入数据。然后将恢复的数据重新存储为新的输入数据。

8. 发明申请

US20130232295A1 ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM 有权
公开(公告)号：US20130232295A1
公开(公告)日：2013-09-05
申请号：US13466861
申请日：2012-05-08
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/126
摘要： Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.

9. 发明申请

US20130046930A1 OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM 有权
标题翻译：优化客户应用程序访问数据的位置与存储系统交互
公开(公告)号：US20130046930A1
公开(公告)日：2013-02-21
申请号：US13606932
申请日：2012-09-07
申请人： Evangelos S. Eleftheriou , Robert Galbraith , Adrian C. Gerhard , Robert Haas , Xiao-Yu Hu , Murali N. Iyer , Ioannis Koltsidas , Timothy J. Larson , Steven P. Norgaard , Roman Pletka
发明人： Evangelos S. Eleftheriou , Robert Galbraith , Adrian C. Gerhard , Robert Haas , Xiao-Yu Hu , Murali N. Iyer , Ioannis Koltsidas , Timothy J. Larson , Steven P. Norgaard , Roman Pletka
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0662 , G06F3/0685
摘要： A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands.
摘要翻译：一种用于优化由与存储系统交互的一个或多个客户端应用访问的物理数据的位置的方法，其中所述存储系统包括具有物理存储器空间和数据带的至少两个冗余组。每个数据带对应于存储在几个物理存储器空间上的物理数据。虚拟化逻辑地址空间包括由一个或多个客户端应用程序可使用的客户机数据地址。存储控制器被配置为将客户端数据地址映射到数据带上，使得获得映射，其中一个或多个客户端应用可以访问对应于数据带的物理数据。

10. 发明申请

US20120278544A1 FLASH MEMORY CONTROLLER 有权
标题翻译：闪存控制器
公开(公告)号：US20120278544A1
公开(公告)日：2012-11-01
申请号：US13515118
申请日：2010-12-09
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
IPC分类号： G06F12/02
CPC分类号： G06F13/1668 , G06F9/3004 , G11C7/1042
摘要： A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.
摘要翻译：闪存控制器通过第一闪存存储器接口耦合到第一闪存存储器封装，并通过第一闪存存储器接口耦合到第二闪存存储器封装。闪存控制器被设计为接收与第一闪存存储器包相关的第一指令，并且根据第一指令执行第一处理。闪存控制器还被设计为接收与第二闪存存储器包相关的第二指令，并且根据第二指令执行第二处理。闪存控制器还适用于将第一进程分成至少两个第一子步骤，并将第二进程分成至少两个第二子步骤。闪存控制器还适用于执行第一和第二子步骤，并且用于交错执行第一和第二子步骤。

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