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1. 发明申请

US20070079079A1 Apparatus, systems and methods to reduce access to shared data storage 有权
标题翻译：减少对共享数据存储的访问的设备，系统和方法
公开(公告)号：US20070079079A1
公开(公告)日：2007-04-05
申请号：US11241249
申请日：2005-09-30
申请人： Xiao-Feng Li , Haibo Lin , Dz-ching Ju
发明人： Xiao-Feng Li , Haibo Lin , Dz-ching Ju
IPC分类号： G06F12/14
CPC分类号： G06F9/5016 , G06F11/3409
摘要： There is provided a method and apparatus to reduce access to shared data storage. The apparatus analyzes a multithreaded application and generates metadata that is utilized to optimize the multithreaded application that executes on multiple processing elements.
摘要翻译：提供了一种减少对共享数据存储的访问的方法和装置。该设备分析多线程应用程序，并生成用于优化在多个处理元素上执行的多线程应用程序的元数据。

2. 发明授权

US08656409B2 High performance queue implementations in multiprocessor systems 失效
标题翻译：多处理器系统中的高性能队列实现
公开(公告)号：US08656409B2
公开(公告)日：2014-02-18
申请号：US12087182
申请日：2005-12-29
申请人： Xiao-Feng Li , Dz-ching Ju
发明人： Xiao-Feng Li , Dz-ching Ju
IPC分类号： G06F9/54
CPC分类号： G06F9/526 , G06F5/12 , G06F9/546 , G06F2209/521
摘要： Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues.
摘要翻译：系统和方法提供单个读写器单写入器（SRSW）队列结构，其具有可以以单一存储器访问以原子方式同时访问的条目。 SRSW队列可以被组合以创建更复杂的队列，包括多个读写器单写入器（MRSW），单个读取器多写入器（SRMW）和多个读取器多写入器（MRMW）队列。

3. 发明申请

US20070226740A1 Method and apparatus for global breakpoint for parallel debugging on multiprocessor systems 审中-公开
标题翻译：用于多处理器系统并行调试的全局断点的方法和装置
公开(公告)号：US20070226740A1
公开(公告)日：2007-09-27
申请号：US11364942
申请日：2006-02-28
申请人： Xiao-Feng Li , Dz-ching Ju
发明人： Xiao-Feng Li , Dz-ching Ju
IPC分类号： G06F9/46
CPC分类号： G06F11/3632
摘要： A system that concurrently executes threads of a multi-threaded application pauses the execution of one thread, then pauses the execution of another thread before the second thread alters a shared memory state. Chipsets and software to implement embodiments of the invention are also described and claimed.
摘要翻译：同时执行多线程应用程序的系统会暂停一个线程的执行，然后在第二个线程改变共享内存状态之前暂停另一个线程的执行。还描述和要求保护用于实现本发明实施例的芯片组和软件。

4. 发明申请

US20070130114A1 METHODS AND APPARATUS TO OPTIMIZE PROCESSING THROUGHPUT OF DATA STRUCTURES IN PROGRAMS 审中-公开
标题翻译：优化程序中数据结构处理的方法与设备
公开(公告)号：US20070130114A1
公开(公告)日：2007-06-07
申请号：US11549745
申请日：2006-10-16
申请人： Xiao-Feng Li , Lixia Liu , Dz-ching Ju
发明人： Xiao-Feng Li , Lixia Liu , Dz-ching Ju
IPC分类号： G06F17/30
CPC分类号： G06F8/4442
摘要： Methods and apparatus to optimize the processing throughput of data structures in programs are disclosed. A disclosed method to automatically optimize processing throughput of a data structure in a program comprises recording information representative of at least one access of the data structure, analyzing the representative information, and modifying the program to optimize the at least one access of the data structure based on the analysis, wherein modifying the program includes modifying at least one instruction of the program to translate one of the at least one access of the data structure from a first memory to a second memory.
摘要翻译：公开了优化程序中数据结构的处理吞吐量的方法和装置。用于自动优化程序中的数据结构的处理吞吐量的公开方法包括记录表示数据结构的至少一次访问的信息，分析代表信息，以及修改程序以优化基于数据结构的至少一个访问在分析中，其中修改程序包括修改程序的至少一个指令以将数据结构的至少一个访问中的一个从第一存储器转换到第二存储器。

5. 发明申请

US20090133023A1 High Performance Queue Implementations in Multiprocessor Systems 失效
标题翻译：多处理器系统中的高性能队列实现
公开(公告)号：US20090133023A1
公开(公告)日：2009-05-21
申请号：US12087182
申请日：2005-12-29
申请人： Xiao-Feng Li , Dz-ching Ju
发明人： Xiao-Feng Li , Dz-ching Ju
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F5/12 , G06F9/546 , G06F2209/521
摘要： Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues.
摘要翻译：系统和方法提供单个读写器单写入器（SRSW）队列结构，其具有可以以单一存储器访问以原子方式同时访问的条目。 SRSW队列可以被组合以创建更复杂的队列，包括多个读写器单写入器（MRSW），单个读取器多写入器（SRMW）和多个读取器多写入器（MRMW）队列。

6. 发明申请

US20060282707A1 Multiprocessor breakpoint 失效
标题翻译：多处理器断点
公开(公告)号：US20060282707A1
公开(公告)日：2006-12-14
申请号：US11148804
申请日：2005-06-09
申请人： Mark Rosenbluth , Xiao-Feng Li , Dz-ching Ju , Aaron Kunze
发明人： Mark Rosenbluth , Xiao-Feng Li , Dz-ching Ju , Aaron Kunze
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system.
摘要翻译：描述可在多处理器系统中使用的技术。在一个实施例中，生成一个或多个信号以指示断点指令由多处理器系统中的多个处理器之一执行。

7. 发明授权

US06782469B1 Runtime critical load/data ordering 失效
标题翻译：运行时关键负载/数据排序
公开(公告)号：US06782469B1
公开(公告)日：2004-08-24
申请号：US09675983
申请日：2000-09-29
申请人： Christopher B. Wilkerson , Srikanth T. Srinivasan , Dz-ching Ju
发明人： Christopher B. Wilkerson , Srikanth T. Srinivasan , Dz-ching Ju
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/383 , G06F9/3838 , G06F9/384
摘要： A critical load ordering unit is responsible for receiving instructions during a critical phase. Load instructions are associated with the number of instructions during the critical phase that depend on the load instructions. The instructions may then be ordered based on their dependence counts and/or marked as critical load instructions.
摘要翻译：关键负载订购单元负责在关键阶段接收指令。加载指令与依赖于加载指令的关键阶段中的指令数量相关联。然后可以基于它们的依赖计数和/或标记为临界负载指令对指令进行排序。

8. 发明授权

US08769509B2 Methods and apparatus for preserving precise exceptions in code reordering by using control speculation 有权
标题翻译：通过使用控制推测在代码重新排序中保留精确异常的方法和装置
公开(公告)号：US08769509B2
公开(公告)日：2014-07-01
申请号：US11937264
申请日：2007-11-08
申请人： Dz-ching Ju
发明人： Dz-ching Ju
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3834 , G06F9/3842
摘要： Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.
摘要翻译：公开了通过使用控制推测在代码重新排序中保持精确异常的方法和装置。所公开的系统使用控制推测模块来重新排序应用程序中的指令并保留精确的异常。如果指令符合某些条件，则控制推测模块可以重新排除除非和除外的指令。当排除指令重新排序时，将检查指令插入程序执行路径，并生成恢复块。检查指令确定重新排序的除外指令是否真的需要生成异常。恢复块包含恢复代码重新排序效果的指令。如果检查指令检测到异常的需要，则执行恢复块以恢复处理器的体系结构状态，并处理异常。

9. 发明授权

US07350024B2 Automatic generation of software-controlled caching and ordered synchronization 有权
标题翻译：自动生成软件控制的缓存和有序同步
公开(公告)号：US07350024B2
公开(公告)日：2008-03-25
申请号：US11015871
申请日：2004-12-16
申请人： Michael Chen , Dz-ching Ju
发明人： Michael Chen , Dz-ching Ju
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F8/4442 , G06F12/0842
摘要： A method for applying software controlled caching and ordered thread optimizations in network applications includes collecting statistics for program variables, selecting program variable candidates for ordered synchronization and/or software controlled cache optimization, performing a safety check to ensure candidates can be properly optimized, and generating code for selected optimization candidates.
摘要翻译：在网络应用中应用软件控制的缓存和有序线程优化的方法包括收集程序变量的统计数据，选择用于有序同步的程序变量候选和/或软件控制的高速缓存优化，执行安全检查以确保候选者能够被适当优化，并产生所选优化候选人的代码。

10. 发明申请

US20080065872A1 METHODS AND APPARATUS FOR PRESERVING PRECISE EXCEPTIONS IN CODE REORDERING BY USING CONTROL SPECULATION 有权
标题翻译：通过使用控制参数在代码重新保存精确异常的方法和装置
公开(公告)号：US20080065872A1
公开(公告)日：2008-03-13
申请号：US11937264
申请日：2007-11-08
申请人： Dz-ching Ju
发明人： Dz-ching Ju
IPC分类号： G06F9/26
CPC分类号： G06F9/3861 , G06F9/3834 , G06F9/3842
摘要： Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.
摘要翻译：公开了通过使用控制推测在代码重新排序中保持精确异常的方法和装置。所公开的系统使用控制推测模块来重新排序应用程序中的指令并保留精确的异常。如果指令符合某些条件，则控制推测模块可以重新排除除非和除外的指令。当排除指令重新排序时，将检查指令插入程序执行路径，并生成恢复块。检查指令确定重新排序的除外指令是否真的需要生成异常。恢复块包含恢复代码重新排序效果的指令。如果检查指令检测到异常的需要，则执行恢复块以恢复处理器的体系结构状态，并处理异常。

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