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1. 发明授权

US06972461B1 Channel MOSFET with strained silicon channel on strained SiGe 失效
标题翻译：通道MOSFET在应变SiGe上具有应变硅通道
公开(公告)号：US06972461B1
公开(公告)日：2005-12-06
申请号：US10710274
申请日：2004-06-30
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang , Huilong Zhu
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/01 , H01L27/11 , H01L29/786
CPC分类号： H01L29/785 , H01L27/11 , H01L27/1108 , H01L29/66795 , H01L29/78687 , Y10S438/933
摘要： A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.
摘要翻译：用作MOSFET的结构采用具有SiGe岛的SOI晶片，其位于SOI层上并在用作源极和漏极的两个块之间延伸; 在SiGe的垂直表面上外延生长的Si形成晶体管沟道。 SiGe的晶格结构被布置成使得外延Si在S和D之间的方向上几乎没有或没有应变，并且垂直于该方向的显着应变。

2. 发明授权

US07102914B2 Gate controlled floating well vertical MOSFET 失效
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US07102914B2
公开(公告)日：2006-09-05
申请号：US10708381
申请日：2004-02-27
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管能够在通常施加到存储和控制单元的两个栅极的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

3. 发明授权

US07045873B2 Dynamic threshold voltage MOSFET on SOI 有权
标题翻译： SOI上的动态阈值电压MOSFET
公开(公告)号：US07045873B2
公开(公告)日：2006-05-16
申请号：US10728750
申请日：2003-12-08
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L29/00
CPC分类号： H01L29/783
摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.
摘要翻译：提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。晶体管配置可以与可以互补对的n型和p型晶体管一起使用。

4. 发明申请

US20060258060A1 Gate controlled floating well vertical MOSFET 审中-公开
标题翻译：门控浮动阱垂直MOSFET
公开(公告)号：US20060258060A1
公开(公告)日：2006-11-16
申请号：US11487809
申请日：2006-07-17
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L21/339
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管在通常施加到存储和控制单元的两个门的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

5. 发明申请

US20050190590A1 GATE CONTROLLED FLOATING WELL VERTICAL MOSFET 失效
标题翻译：门控浮动井垂直MOSFET
公开(公告)号：US20050190590A1
公开(公告)日：2005-09-01
申请号：US10708381
申请日：2004-02-27
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： G11C11/24 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/10841
摘要： A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.
摘要翻译：用于DRAM单元的新型晶体管结构包括两个深沟槽，一个沟槽包括用于存储数据的垂直存储单元，第二沟槽包括用于控制p阱电压的垂直控制单元，其实际上将部分 p阱处于浮置状态，从而与垂直传输晶体管处于截止状态时相比降低阈值电压。这使得晶体管能够在通常施加到存储和控制单元的两个栅极的有效字线电压期间表现出增加的栅极过驱动和驱动电流。

6. 发明申请

US20050121699A1 Dynamic threshold voltage MOSFET on SOI 有权
标题翻译： SOI上的动态阈值电压MOSFET
公开(公告)号：US20050121699A1
公开(公告)日：2005-06-09
申请号：US10728750
申请日：2003-12-08
申请人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Geng Wang
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/085 , H01L27/092 , H01L27/12 , H01L29/745 , H01L29/78 , H01L29/786
CPC分类号： H01L29/783
摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.
摘要翻译：提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。晶体管配置可以与可以互补对的n型和p型晶体管一起使用。

7. 发明授权

US07002209B2 MOSFET structure with high mechanical stress in the channel 有权
标题翻译： MOSFET结构在通道中具有高机械应力
公开(公告)号：US07002209B2
公开(公告)日：2006-02-21
申请号：US10851830
申请日：2004-05-21
申请人： Xiangdong Chen , Dureseti Chidambarrao , Oleg Gluschenkov , Brian Greene , Kern Rim , Haining S. Yang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Oleg Gluschenkov , Brian Greene , Kern Rim , Haining S. Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.
摘要翻译：本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力。在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。本发明还提供了形成上述半导体器件的方法。

8. 发明申请

US20050260808A1 MOSFET structure with high mechanical stress in the channel 有权
标题翻译： MOSFET结构在通道中具有高机械应力
公开(公告)号：US20050260808A1
公开(公告)日：2005-11-24
申请号：US10851830
申请日：2004-05-21
申请人： Xiangdong Chen , Dureseti Chidambarrao , Oleg Gluschenkov , Brian Greene , Kern Rim , Haining Yang
发明人： Xiangdong Chen , Dureseti Chidambarrao , Oleg Gluschenkov , Brian Greene , Kern Rim , Haining Yang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.
摘要翻译：本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力。在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。本发明还提供了形成上述半导体器件的方法。

9. 发明申请

US20070045611A1 MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：具有横向分级通道区域的MOSFET及其制造方法
公开(公告)号：US20070045611A1
公开(公告)日：2007-03-01
申请号：US11162126
申请日：2005-08-30
申请人： Huilong Zhu , Xiangdong Chen
发明人： Huilong Zhu , Xiangdong Chen
IPC分类号： H01L29/06
CPC分类号： H01L21/26506 , H01L21/28132 , H01L29/1054 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7834 , H01L29/78684 , H01L29/78696
摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.
摘要翻译：本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级到半导体器件所在的衬底表面。具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

10. 发明申请

US20090014794A1 MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：具有横向分级通道区域的MOSFET及其制造方法
公开(公告)号：US20090014794A1
公开(公告)日：2009-01-15
申请号：US12238041
申请日：2008-09-25
申请人： Huilong Zhu , Xiangdong Chen
发明人： Huilong Zhu , Xiangdong Chen
IPC分类号： H01L47/00
CPC分类号： H01L21/26506 , H01L21/28132 , H01L29/1054 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7834 , H01L29/78684 , H01L29/78696
摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.
摘要翻译：本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级到半导体器件所在的衬底表面。具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

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