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1. 发明授权

US08074110B2 Enhancing reliability of a many-core processor 有权
标题翻译：提高多核处理器的可靠性
公开(公告)号：US08074110B2
公开(公告)日：2011-12-06
申请号：US12224108
申请日：2006-02-28
申请人： Xavier Vera , Osman Unsal , Oguz Ergin , Jaume Abella , Antonio González
发明人： Xavier Vera , Osman Unsal , Oguz Ergin , Jaume Abella , Antonio González
IPC分类号： G06F11/00
CPC分类号： G06F1/206 , G06F9/5061 , G06F9/5094 , G06F11/202 , Y02D10/22
摘要： In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于识别多核处理器的可用核心的方法，将核心的第一子集分配给启用状态，将核心的第二子集分配到备用状态，以及存储关于分配的信息在一个存储。在某些实施例中，将核分配到启用状态可以基于温度感知算法。描述和要求保护其他实施例。

2. 发明授权

US08151094B2 Dynamically estimating lifetime of a semiconductor device 有权
标题翻译：动态估计半导体器件的寿命
公开(公告)号：US08151094B2
公开(公告)日：2012-04-03
申请号：US12086357
申请日：2005-12-30
申请人： Xavier Vera , Jaume Abella , Osman Unsal , Oguz Ergin , Antonio González
发明人： Xavier Vera , Jaume Abella , Osman Unsal , Oguz Ergin , Antonio González
IPC分类号： G06F11/30
CPC分类号： G06F11/008 , G01R31/2846
摘要： The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operating parameter information, and dynamically estimating a remaining lifetime of the device based on the dynamic usage. Depending on the estimated remaining lifetime, the device may be controlled in a desired manner.
摘要翻译：本发明包括一种用于获得诸如处理器的半导体器件的动态操作参数信息的方法，基于动态操作参数信息来确定整个或一个或多个部分的设备的动态使用，并动态地基于动态使用估计设备的剩余寿命。根据估计的剩余寿命，可以以期望的方式控制装置。

3. 发明申请

US20120047398A1 Detecting Soft Errors Via Selective Re-Execution 有权
标题翻译：通过选择性重新执行检测软错误
公开(公告)号：US20120047398A1
公开(公告)日：2012-02-23
申请号：US13284086
申请日：2011-10-28
申请人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
发明人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
IPC分类号： G06F11/14
CPC分类号： G06F11/008 , G06F11/1497
摘要： In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在处理器中执行的指令的漏洞级别的方法，以及如果漏洞级别高于阈值则重新执行该指令。漏洞级别可能对应于指令在处理器中时指令的软错误可能性。描述和要求保护其他实施例。

4. 发明授权

US08090996B2 Detecting soft errors via selective re-execution 有权
标题翻译：通过选择性重新执行检测软错误
公开(公告)号：US08090996B2
公开(公告)日：2012-01-03
申请号：US12224762
申请日：2006-03-31
申请人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
发明人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
IPC分类号： G06F11/00 , G06F11/30
CPC分类号： G06F11/008 , G06F11/1497
摘要： In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在处理器中执行的指令的漏洞级别的方法，以及如果漏洞级别高于阈值则重新执行该指令。漏洞级别可能对应于指令在处理器中时指令的软错误可能性。描述和要求保护其他实施例。

5. 发明授权

US08402310B2 Detecting soft errors via selective re-execution 有权
标题翻译：通过选择性重新执行检测软错误
公开(公告)号：US08402310B2
公开(公告)日：2013-03-19
申请号：US13284086
申请日：2011-10-28
申请人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
发明人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/008 , G06F11/1497
摘要： In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在处理器中执行的指令的漏洞级别的方法，以及如果漏洞级别高于阈值则重新执行该指令。漏洞级别可能对应于指令在处理器中时指令的软错误可能性。描述和要求保护其他实施例。

6. 发明授权

US07558992B2 Reducing the soft error vulnerability of stored data 有权
标题翻译：减少存储数据的软错误漏洞
公开(公告)号：US07558992B2
公开(公告)日：2009-07-07
申请号：US10563169
申请日：2005-10-10
申请人： Oguz Ergin , Osman Unsal , Xavier Vera , Antonio González
发明人： Oguz Ergin , Osman Unsal , Xavier Vera , Antonio González
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G06F11/1666
摘要： Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.
摘要翻译：公开了用于减少存储数据的软错误脆弱性的装置和方法的实施例。在一个实施例中，一种装置包括存储逻辑，确定逻辑和选择逻辑。确定逻辑是确定数据字的条件。存储逻辑包括用于存储数据字的第一部分，数据字的第二部分以及由确定逻辑产生的结果的逻辑。选择逻辑是基于用于存储结果的存储逻辑的内容来选择存储逻辑的内容来存储数据字的第二部分或替换值。替换值取决于存储逻辑的预定位的内容以存储数据字的第一部分。

7. 发明授权

US08477558B2 Memory apparatuses with low supply voltages 有权
标题翻译：具有低电源电压的存储设备
公开(公告)号：US08477558B2
公开(公告)日：2013-07-02
申请号：US12262070
申请日：2008-10-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
IPC分类号： G11C8/00
CPC分类号： G06F13/4234 , G06F12/0802 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
摘要翻译：提供了低电压存储装置。在一个实施例中，存储器装置包括存储器和存储器控制器。存储器控制器包括读控制器。读取控制器防止对存储器位置的读取操作在对存储器位置的写入操作之后至少N个时钟周期完成，其中N是在写入操作之后存储器位置稳定的时钟周期数。

8. 发明授权

US08352812B2 Protecting data storage structures from intermittent errors 有权
标题翻译：保护数据存储结构免受间歇性错误的影响
公开(公告)号：US08352812B2
公开(公告)日：2013-01-08
申请号：US11833765
申请日：2007-08-03
申请人： Xavier Vera , Jaume Abella , Javier Carretero Casado , Antonio González
发明人： Xavier Vera , Jaume Abella , Javier Carretero Casado , Antonio González
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1405
摘要： Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.
摘要翻译：公开了用于保护数据存储结构免于间歇性错误的装置和方法的实施例。在一个实施例中，装置包括多个数据存储位置，执行逻辑，错误检测逻辑和控制逻辑。执行逻辑是执行指令以生成数据值以存储在数据存储位置之一中。错误检测逻辑是检测数据存储位置中存储的数据值中的错误。控制逻辑是通过使执行逻辑重新执行用于重新生成数据值以存储在数据存储位置的指令来响应错误的检测，使得错误检测逻辑检查从数据读取的数据值存储位置，如果检测到另一个错误，则停用数据存储位置。

9. 发明授权

US07313675B2 Register allocation technique 失效
标题翻译：注册分配技术
公开(公告)号：US07313675B2
公开(公告)日：2007-12-25
申请号：US11155755
申请日：2005-06-16
申请人： Fernando Latorre , José González , Antonio González
发明人： Fernando Latorre , José González , Antonio González
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for allocating register resources within a microprocessor. More particularly, embodiments of the invention pertain to a register allocation technique within a microprocessor for multiple-threads of instructions or groups of micro-operations (“uops”).
摘要翻译：一种用于在微处理器内分配寄存器资源的技术。更具体地，本发明的实施例涉及用于多线程指令或微操作组（“uops”）的微处理器内的寄存器分配技术。

10. 发明授权

US08612698B2 Replacement policy for hot code detection 有权
标题翻译：热代码检测替代策略
公开(公告)号：US08612698B2
公开(公告)日：2013-12-17
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
发明人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译：描述与热代码检测的替换策略有关的方法和装置。在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。还描述和要求保护其他实施例。

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