专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0902398B1 Method and system for compressing and decompressing binary representations of dithered images 有权
标题翻译：对于Halbtonzitterbildern的压缩和解压缩的方法和设备
公开(公告)号：EP0902398B1
公开(公告)日：2003-07-02
申请号：EP98307215.8
申请日：1998-09-07
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06T9/00
CPC分类号： G06T9/001 , H04N1/4105

2. 发明公开

EP1001605A2 Document processing 有权
标题翻译：文档处理
公开(公告)号：EP1001605A2
公开(公告)日：2000-05-17
申请号：EP99308879.8
申请日：1999-11-08
申请人： Xerox Corporation
发明人： Klotz, Leigh L., Jr. , Petrie, Glen W. , Bauer, Robert S. , Davies, Daniel , Craig, Julia A.
IPC分类号： H04N1/32
CPC分类号： H04N1/32133 , H04N1/00968 , H04N2201/3205 , H04N2201/3222 , H04N2201/3269
摘要： A tag-based user interface scheme for digitizing and processing hardcopy documents utilizes a sticker (110) that includes a printed data code representative of a user identity code (118) and a service code (112). When the sticker is applied to a hardcopy document and scanned, the sticker is located, the data code is parsed, and a desired service is performed based upon the information stored in the data code.

3. 发明授权

EP0602887B1 Performing arithmetic on composite operands 失效
标题翻译：对操作数zusammegestellten执行算术
公开(公告)号：EP0602887B1
公开(公告)日：2000-03-15
申请号：EP93309862.6
申请日：1993-12-08
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06F7/48 , G06F7/50
CPC分类号： G06F7/505 , G06F7/02 , G06F7/026 , G06F7/48 , G06F7/49905 , G06F9/30021 , G06F9/30036 , G06F2207/3828 , G06F2207/386

4. 发明授权

EP0602888B1 Performing arithmetic operations on data 失效
标题翻译：数据实现aritmetische操作
公开(公告)号：EP0602888B1
公开(公告)日：1999-09-08
申请号：EP93309863.4
申请日：1993-12-08
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06F7/48 , G06F7/50
CPC分类号： G06F7/505 , G06F7/48 , G06F9/30036 , G06F2207/3828 , G06F2207/386

5. 发明公开

EP0602887A1 Performing arithmetic on composite operands 失效
标题翻译： Durchführungvon Arithmetik auf zusammegestellten Operanden。
公开(公告)号：EP0602887A1
公开(公告)日：1994-06-22
申请号：EP93309862.6
申请日：1993-12-08
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06F7/48 , G06F7/50
CPC分类号： G06F7/505 , G06F7/02 , G06F7/026 , G06F7/48 , G06F7/49905 , G06F9/30021 , G06F9/30036 , G06F2207/3828 , G06F2207/386
摘要： Binary outcome operations are performed on composite operands. A composite operand (10) is an operand that includes plural multi-bit component data items (12,14,16). A binary outcome operation obtains, for each component, a flag bit (32,34,36) that depends on the numerical value of the component. A binary outcome operation can be performed by performing an arithmetic operation in parallel on a composite operand (10) in which each component includes more than one bit. The arithmetic operation can add a value, producing a carry signal if a component and the added value together exceed a maximum possible value. Or the arithmetic operation can subtract a value, producing a borrow signal if a component is less than the subtracted value. Also, if the arithmetic operation subtracts a value that is equal to the component, the resulting data item includes only zeros; an operation in parallel can then obtain a single flag bit that is a zero only if the resulting data item includes only zeros. The binary outcome operation can compare each component with a value or can determine whether each component is within a range.
摘要翻译：二进制结果操作在复合操作数上执行。合成操作数（10）是包括多个多位分量数据项（12,14,16）的操作数。对于每个组件，二进制结果操作获得取决于组件的数值的标志位（32,34,36）。可以通过在其中每个分量包括多于一个位的合成操作数（10）上并行执行算术运算来执行二进制结果操作。算术运算可以添加一个值，如果一个分量和一个加法值一起超过一个最大可能值，产生一个进位信号。或者算术运算可以减去一个值，如果一个分量小于减去的值，产生借位信号。此外，如果算术运算减去与分量相等的值，则生成的数据项仅包括零; 然后并行的操作可以获得仅当所得到的数据项仅包括零时为零的单个标志位。二进制结果操作可以将每个组件与值进行比较，或者可以确定每个组件是否在一个范围内。

6. 发明授权

EP1001605B1 Document processing 有权
标题翻译：文档处理
公开(公告)号：EP1001605B1
公开(公告)日：2007-03-07
申请号：EP99308879.8
申请日：1999-11-08
申请人： Xerox Corporation
发明人： Klotz, Leigh L., Jr. , Petrie, Glen W. , Bauer, Robert S. , Davies, Daniel , Craig, Julia A.
IPC分类号： H04N1/32
CPC分类号： H04N1/32133 , H04N1/00968 , H04N2201/3205 , H04N2201/3222 , H04N2201/3269

7. 发明公开

EP0431961A3 Image reduction/enlargement technique 失效
标题翻译：图像减少/扩展技术
公开(公告)号：EP0431961A3
公开(公告)日：1993-02-24
申请号：EP90313312.2
申请日：1990-12-07
申请人： XEROX CORPORATION
发明人： Bloomberg, Dan S. , Davies, Daniel
IPC分类号： G06F15/62 , G06F15/68
CPC分类号： G06T3/4023
摘要： A method of reducing an M X N input binary image (M rows of N pixels each) by a factor of m vertically and n horizontally includes the steps of performing at least one logical operation between bits in consecutive groups of m adjacent rows to provide a resultant single row for each group of m rows, and performing at least adjacent columns to provide a resultant single column for each groups of n columns. For certain types of reductions the resulting reduced image will be the desired output image, while for other types, the resultant image will be one of a required plurality of intermediate images, which are then combined to provide the desired output image.

8. 发明授权

EP0431961B1 Image reduction/enlargement technique 失效
标题翻译：技术图像缩小和放大
公开(公告)号：EP0431961B1
公开(公告)日：1998-08-12
申请号：EP90313312.2
申请日：1990-12-07
申请人： XEROX CORPORATION
发明人： Bloomberg, Dan S. , Davies, Daniel
IPC分类号： G06T3/40
CPC分类号： G06T3/4023

9. 发明公开

EP0602915A3 SIMD architecture for connection to host processor's bus 失效
标题翻译：用于连接到主处理器总线的SIMD架构。
公开(公告)号：EP0602915A3
公开(公告)日：1996-01-24
申请号：EP93309997.0
申请日：1993-12-10
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06F15/16 , G06F9/38
CPC分类号： G06F15/17 , G06F9/30036 , G06F9/3881 , G06F9/3887
摘要： A coprocessor (20) includes processing units (22), control circuitry (24), and circuitry (30) for connecting the coprocessor to a host processor (10). The connecting circuitry (30) includes slave circuitry (32) and master circuitry (34). The slave circuitry (32) receives requests for coprocessor operations from the host processor's bus (12) and provides signals to the control circuitry (24) so that requested operations are performed. The master circuitry (34) receives requests for data transfer operations from the control circuitry (24); the master circuitry requests host bus operations and also transfers data between the coprocessor and the host bus to perform requested data transfer operations. The control circuitry (24) includes a control/status register and a control store. The slave circuitry (32) can change data in the control/status register or transfer data from the control/status register to the host bus. The slave circuitry can also transfer data between the host bus and the control store. The master circuitry (34) includes a bus connected to each of the processing units through a register and connected to the host bus through a pipeline of registers. The master circuitry can provide an address or data to be written to the host bus from any of the processing units, and can provide data being read from the host bus to each of a set of processing units. The master circuitry can perform single word or multi-word DMA read and write operations, and can also use the control store as a mailbox for communication with the host processor or other host bus masters. The processing units can operate on data in horizontal format so that corner turning is unnecessary.

10. 发明公开

EP0602888A1 Performing arithmetic operations on data 失效
标题翻译： Durchführungaritmetische Operationen auf Daten。
公开(公告)号：EP0602888A1
公开(公告)日：1994-06-22
申请号：EP93309863.4
申请日：1993-12-08
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06F7/48 , G06F7/50
CPC分类号： G06F7/505 , G06F7/48 , G06F9/30036 , G06F2207/3828 , G06F2207/386
摘要： Arithmetic operations are performed on composite operands that include plural component data items. The operations obtain valid results even though the operations would ordinarily produce inter-component signals, such as carry or borrow signals or a shifted bit, causing invalid results. For example, the component data items can be pixel values or other data relating to pixels in an image. Instructions on a storage medium (62) can be accessed and executed by a processor (66) to obtain valid results despite inter-component signals. Or special circuitry, such as gating circuitry or a mask register, can be used to prevent inter-component signals. Components in composite operands can be separated by buffer bits that are cleared or set to ensure valid results. Values of components can be biased before an operation to obtain valid results.
摘要翻译：对包含多个组件数据项的复合操作数执行算术运算。即使操作通常产生分量间信号，例如进位或借位信号或偏移位，导致无效结果，操作获得有效结果。例如，分量数据项可以是与图像中的像素相关的像素值或其他数据。存储介质（62）上的指令可由处理器（66）访问和执行，以获得尽管分量间信号的有效结果。或者可以使用诸如门控电路或屏蔽寄存器的特殊电路来防止分量间信号。复合操作数中的组件可以被清除或设置为保证有效结果的缓冲区分隔开。组件的值可以在操作之前被偏置以获得有效的结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式