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1. 发明授权

US09917094B2 Semiconductor device having staggered pillars 有权
公开(公告)号：US09917094B2
公开(公告)日：2018-03-13
申请号：US14920223
申请日：2015-10-22
申请人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
发明人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
IPC分类号： G11C5/06 , H01L27/11565 , G11C7/00 , H01L23/48 , G11C7/18 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/02
CPC分类号： H01L27/11565 , G11C5/06 , G11C5/063 , G11C7/00 , G11C7/18 , H01L23/48 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

2. 发明授权

US09177613B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09177613B2
公开(公告)日：2015-11-03
申请号：US14018885
申请日：2013-09-05
申请人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
发明人： Wookhyoung Lee , Jongsik Chun , Sunil Shim , Jaeyoung Ahn , Juyul Lee , Kihyun Hwang , Hansoo Kim , Woonkyung Lee , Jaehoon Jang , Wonseok Cho
IPC分类号： G11C5/06 , G11C7/00 , H01L23/48 , G11C7/18 , H01L27/115 , H01L27/02
CPC分类号： H01L27/11565 , G11C5/06 , G11C5/063 , G11C7/00 , G11C7/18 , H01L23/48 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.
摘要翻译：提供了一种半导体器件，其包括设置在基板上的栅极结构，插入在栅极结构之间的分离绝缘层以及通过每个栅极结构连接到基板的多个单元柱。每个栅极结构可以包括垂直堆叠在基板上的水平电极，并且相邻的单元柱之间的间隔是不均匀的。

3. 发明申请

US20100109065A1 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES 有权
标题翻译：具有分包活性棒的三维非易失性存储器件及其制造方法
公开(公告)号：US20100109065A1
公开(公告)日：2010-05-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

4. 发明授权

US08426301B2 Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices 有权
标题翻译：具有分割活动杆的三维非易失性存储器件及其制造方法
公开(公告)号：US08426301B2
公开(公告)日：2013-04-23
申请号：US13197026
申请日：2011-08-03
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L21/4763
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

5. 发明申请

US20110287623A1 Three-Dimensional Nonvolatile Memory Devices Having Sub-Divided Active Bars and Methods of Manufacturing Such Devices 有权
标题翻译：具有子分割活动条的三维非易失性存储器件及其制造方法
公开(公告)号：US20110287623A1
公开(公告)日：2011-11-24
申请号：US13197026
申请日：2011-08-03
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

6. 发明授权

US08013389B2 Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices 有权
标题翻译：具有分割活动杆的三维非易失性存储器件及其制造方法
公开(公告)号：US08013389B2
公开(公告)日：2011-09-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L29/66
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

7. 发明申请

US20140035026A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20140035026A1
公开(公告)日：2014-02-06
申请号：US13800872
申请日：2013-03-13
申请人： Byong-hyun Jang , Juhyung Kim , Woonkyung Lee , Jaegoo Lee , Chaeho Kim , Junkyu Yang , Phil Ouk Nam , Jaeyoung Ahn , Kihyun Hwang
发明人： Byong-hyun Jang , Juhyung Kim , Woonkyung Lee , Jaegoo Lee , Chaeho Kim , Junkyu Yang , Phil Ouk Nam , Jaeyoung Ahn , Kihyun Hwang
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L23/528 , H01L27/1157 , H01L27/11582 , H01L29/045 , H01L29/1037 , H01L29/42364 , H01L29/511 , H01L29/66833 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.
摘要翻译：一种半导体存储器件及其制造方法。该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道和大门。外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。

8. 发明申请

US20140014889A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140014889A1
公开(公告)日：2014-01-16
申请号：US13938833
申请日：2013-07-10
申请人： Sunil Shim , Wonseok Cho , Woonkyung Lee
发明人： Sunil Shim , Wonseok Cho , Woonkyung Lee
IPC分类号： H01L29/78 , H01L45/00 , H01L23/538
CPC分类号： H01L27/11582 , H01L23/5384 , H01L27/11556 , H01L27/11565 , H01L27/2409 , H01L27/2481 , H01L27/249 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
摘要翻译：半导体器件包括多个第一绝缘层和多个第二层，其交替地和垂直地堆叠在基板上。多个第二层中的每一个包括由第二绝缘层水平隔开的水平电极。接触插塞穿透多个第二绝缘层和多个第二层中的第二绝缘层。

9. 发明授权

US08873294B2 Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US08873294B2
公开(公告)日：2014-10-28
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , H01L29/792 , G11C16/30 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

10. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

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