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1. 发明授权

US06451691B2 Methods of manufacturing a metal pattern of a semiconductor device which include forming nitride layer at exposed sidewalls of Ti layer of the pattern 失效
标题翻译：制造半导体器件的金属图案的方法，其包括在图案的Ti层的暴露的侧壁处形成氮化物层
公开(公告)号：US06451691B2
公开(公告)日：2002-09-17
申请号：US09794616
申请日：2001-02-28
申请人： Won-Sang Song , In-Sun Park , Kyung-Bum Koo , Young-Cheon Kim
发明人： Won-Sang Song , In-Sun Park , Kyung-Bum Koo , Young-Cheon Kim
IPC分类号： H01L2144
CPC分类号： H01L21/76885 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76852 , H01L21/76856 , H01L21/76867
摘要： A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.
摘要翻译：一种制造半导体器件的金属图案的方法。在半导体衬底或绝缘层上依次形成Ti层和金属层。然后，通过图案化所述Ti层和金属层来形成包括Ti层图案和金属层图案的布线图案。在包括氮的化合物的气氛下进行热处理，以使Ti层图案的暴露部分反应形成TiN作为主要产物，从而提高后续工艺中金属层的稳定性和粘附性。

2. 发明授权

US06797575B2 Method for forming a polycide structure in a semiconductor device 失效
标题翻译：在半导体器件中形成多晶硅结构的方法
公开(公告)号：US06797575B2
公开(公告)日：2004-09-28
申请号：US10101209
申请日：2002-03-20
申请人： Young-Cheon Kim , In-Sun Park , Ju-Cheol Shin
发明人： Young-Cheon Kim , In-Sun Park , Ju-Cheol Shin
IPC分类号： H01L21336
CPC分类号： H01L21/32053
摘要： A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.
摘要翻译：防止多晶硅结构中的空隙形成的方法包括依次沉积栅极氧化膜，掺杂杂质的多晶硅膜，具有足够量硅的种子膜以与覆盖钨层反应，硅化钨前体层; 以及由半导体衬底上的绝缘材料制成的蚀刻掩模; 使用所述蚀刻掩模进行图案化蚀刻; 并在氧气氛中在升高的温度和压力下对所得结构进行热处理，以形成防止空隙形成的多晶硅结构。由于种子膜具有足够量的用于与钨反应的非晶硅，所以可防止硅原子迁移到多晶硅膜与硅化钨前体层之间的界面，从而防止在多晶硅膜中形成空隙。

3. 发明授权

US06623798B2 Chemical vapor deposition method for depositing silicide and apparatus for performing the same 有权
公开(公告)号：US06623798B2
公开(公告)日：2003-09-23
申请号：US09884993
申请日：2001-06-21
申请人： Ju-Cheol Shin , In-Sun Park , Young-Cheon Kim , Chul Whang-Bo , Hyeon-Deok Lee
发明人： Ju-Cheol Shin , In-Sun Park , Young-Cheon Kim , Chul Whang-Bo , Hyeon-Deok Lee
IPC分类号： C23C1642
CPC分类号： C23C16/4412 , C23C16/42 , C23C16/54
摘要： A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.

4. 发明授权

US06740587B2 Semiconductor device having a metal silicide layer and method for manufacturing the same 有权
标题翻译：具有金属硅化物层的半导体器件及其制造方法
公开(公告)号：US06740587B2
公开(公告)日：2004-05-25
申请号：US09949853
申请日：2001-09-12
申请人： Won-Sang Song , Jeong-Hwan Yang , In-Sun Park , Byoung-Moon Yoon
发明人： Won-Sang Song , Jeong-Hwan Yang , In-Sun Park , Byoung-Moon Yoon
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/32053 , H01L21/76895 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device having a metal suicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.
摘要翻译：本发明提供一种具有金属硅化物层的半导体器件和用于形成金属硅化物层的方法，该半导体器件具有金属硅化物半导体接触结构，其中半导体器件包括衬底，具有开口的绝缘层，使用具有第一相和第二相的天然金属硅化物形成金属硅化物层，在其上形成导电层。第二相具有与第一相的第二化学计量组成比不同的第一化学计量组成比。第一相的金属硅化物层与硅之间的反应导致第二相的金属硅化物层具有高相稳定性和低电阻。

5. 发明授权

US07504725B2 Semiconductor memory device having low-resistance tungsten line and method of manufacturing the semiconductor memory device 有权
标题翻译：具有低电阻钨线的半导体存储器件及半导体存储器件的制造方法
公开(公告)号：US07504725B2
公开(公告)日：2009-03-17
申请号：US10915871
申请日：2004-08-09
申请人： Rak-Hwan Kim , Young-Cheon Kim , Hyeon-Deok Lee , Hyun-Young Kim , In-Sun Park
发明人： Rak-Hwan Kim , Young-Cheon Kim , Hyeon-Deok Lee , Hyun-Young Kim , In-Sun Park
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/28556 , H01L21/76841 , H01L21/76846 , H01L21/7685 , H01L21/76862 , H01L21/76876 , H01L27/10885 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.
摘要翻译：一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。沿着绝缘层的表面和接触孔的表面形成阻挡金属层。在阻挡金属层与钨层之间形成晶粒控制层。在晶粒控制层上形成钨层。钨层的晶粒尺寸由晶粒控制层增加。

6. 发明申请

US20050042829A1 Semiconductor memory device having low-resistance tungsten line and method of manufacturing the semiconductor memory device 有权
标题翻译：具有低电阻钨线的半导体存储器件及半导体存储器件的制造方法
公开(公告)号：US20050042829A1
公开(公告)日：2005-02-24
申请号：US10915871
申请日：2004-08-09
申请人： Rak-Hwan Kim , Young-Cheon Kim , Hyeon-Deok Lee , Hyun-Young Kim , In-Sun Park
发明人： Rak-Hwan Kim , Young-Cheon Kim , Hyeon-Deok Lee , Hyun-Young Kim , In-Sun Park
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/485
CPC分类号： H01L23/485 , H01L21/28556 , H01L21/76841 , H01L21/76846 , H01L21/7685 , H01L21/76862 , H01L21/76876 , H01L27/10885 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.
摘要翻译：一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。沿着绝缘层的表面和接触孔的表面形成阻挡金属层。在阻挡金属层与钨层之间形成晶粒控制层。在晶粒控制层上形成钨层。钨层的晶粒尺寸由晶粒控制层增加。

7. 发明申请

US20060281289A1 Method of forming polycide layer and method of manufacturing semiconductor device having polycide layer 审中-公开
标题翻译：形成聚酰亚胺层的方法和制造具有多晶硅化物层的半导体器件的方法
公开(公告)号：US20060281289A1
公开(公告)日：2006-12-14
申请号：US11446981
申请日：2006-06-06
申请人： Young-Cheon Kim , Chul Hwangbo , Rak-Hwan Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
发明人： Young-Cheon Kim , Chul Hwangbo , Rak-Hwan Kim , Hyeon-Deok Lee , In-Sun Park , Ji-Soon Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/26513 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4933 , H01L29/6659 , H01L29/7833
摘要： In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.
摘要翻译：在形成多晶硅化合物层的方法和制造具有多晶硅化物层的半导体器件的方法中，该方法可以包括在具有第一区域和第二区域的衬底上形成掺杂有第一类型杂质的初步多晶硅层，杂质进入第二区域的初步多晶硅层的一部分，热处理初步多晶硅层以电激活杂质，去除热处理的初步多晶硅层的上表面的一部分以获得多晶硅层，形成金属硅化物并且在所述第一区域上形成所述多晶硅层和所述金属硅化物层以形成第一类型的栅电极，并在所述第二区域上形成第二类型的栅电极。

8. 发明申请

US20090008623A1 Methods of fabricating nonvolatile memory device and a nonvolatile memory device 审中-公开
标题翻译：制造非易失性存储器件和非易失性存储器件的方法
公开(公告)号：US20090008623A1
公开(公告)日：2009-01-08
申请号：US12216004
申请日：2008-06-27
申请人： Hyun-Seok Lim , In-Sun Park , Gyu-Hwan Oh , Do-Hyung Kim , Shin-Jae Kang
发明人： Hyun-Seok Lim , In-Sun Park , Gyu-Hwan Oh , Do-Hyung Kim , Shin-Jae Kang
IPC分类号： H01L47/00 , H01L21/311
CPC分类号： H01L21/28518 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： Methods of fabricating a nonvolatile memory device using a resistance material and a nonvolatile memory device are provided. According to example embodiments, a method of fabricating a nonvolatile memory device may include forming at least one semiconductor pattern on a substrate, forming a metal layer on the at least one semiconductor pattern, forming a mixed-phase metal silicide layer, in which at least two phases coexist, by performing at least one heat treatment on the substrate so that the at least one semiconductor pattern may react with the metal layer, and exposing the substrate to an etching gas.
摘要翻译：提供使用电阻材料制造非易失性存储器件和非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底上形成至少一个半导体图案，在至少一个半导体图案上形成金属层，形成混合相金属硅化物层，其中至少两相共存，通过在基板上进行至少一次热处理，使得至少一个半导体图案可与金属层反应，并使基板暴露于蚀刻气体。

9. 发明申请

US20080230373A1 METHODS OF FORMING A PHASE-CHANGE MATERIAL LAYER INCLUDING TELLURIUM AND METHODS OF MANUFACTURING A PHASE-CHANGE MEMORY DEVICE USING THE SAME 有权
标题翻译：形成相变材料层的方法及其制造方法使用该方法的相变存储器件
公开(公告)号：US20080230373A1
公开(公告)日：2008-09-25
申请号：US12051043
申请日：2008-03-19
申请人： Do-Hyung Kim , Shin-Jae Kang , In-Sun Park , Hyun-Seok Lim , Gyu-Hwan Oh
发明人： Do-Hyung Kim , Shin-Jae Kang , In-Sun Park , Hyun-Seok Lim , Gyu-Hwan Oh
IPC分类号： C23C14/34
CPC分类号： C23C14/3414 , C23C14/0623 , G11B7/2433 , G11B7/252 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.
摘要翻译：本发明提供了形成相变材料层的方法，包括在碲被挥发并且锑不挥发的温度下提供包括锗（Ge），锑（Sb）和碲（Te）的基板和硫族化物靶，以及进行溅射工艺以在衬底上形成包括硫族化物材料的相变材料层。还提供了制造使用其的相变存储器件的方法。

10. 发明授权

US07122468B2 Methods of fabricating integrated circuit conductive contact structures including grooves 有权
标题翻译：制造集成电路导电接触结构包括沟槽的方法
公开(公告)号：US07122468B2
公开(公告)日：2006-10-17
申请号：US11039562
申请日：2005-01-20
申请人： Ju-Cheol Shin , Hyeon-Deok Lee , Hong-Mi Park , In-Sun Park
发明人： Ju-Cheol Shin , Hyeon-Deok Lee , Hong-Mi Park , In-Sun Park
IPC分类号： H01L21/4763
CPC分类号： H01L27/10894 , H01L21/76877 , H01L23/5226 , H01L27/10817 , H01L27/10885 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.
摘要翻译：集成电路包括衬底和衬底上的第一绝缘层，其包括包括地板和侧壁的第一孔。第一导电接触件在侧壁和底板上保形地延伸以在第一孔中限定凹槽。第二绝缘层设置在第一绝缘层上，并且包括露出槽的第二孔。在第二孔和凹槽中设置第二导电接触。这些集成电路通过在基板上形成第一绝缘层来制造，所述第一绝缘层包括包括地板和侧壁的第一孔。第一导电接触共形地形成在侧壁和地板上以在第一孔中限定凹槽。第二绝缘层形成在第一绝缘层上，并且包括暴露槽的第二孔。在第二孔和槽中形成第二导电接触。

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