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1. 发明申请

US20070018237A1 Non-volatile memory device having fin-type channel region and method of fabricating the same 审中-公开
标题翻译：具有鳍型沟道区的非易失性存储器件及其制造方法
公开(公告)号：US20070018237A1
公开(公告)日：2007-01-25
申请号：US11489445
申请日：2006-07-20
申请人： Won-Joo Kim , Suk-Pil Kim , Yoon-Dong Park , Eun-Hong Lee , Jae-Woong Hyun , Sung-Jae Byun , Jung-Hoon Lee
发明人： Won-Joo Kim , Suk-Pil Kim , Yoon-Dong Park , Eun-Hong Lee , Jae-Woong Hyun , Sung-Jae Byun , Jung-Hoon Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/7851 , H01L29/792
摘要： A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair of fins protruding from a body and extending, spaced from each other along one direction, as at least one pair of channel regions. At least one control gate electrode may be formed across the channel regions, and at least one pair of storage nodes may be interposed in at least one portion between the control gate electrode and the channel regions.
摘要翻译：具有通过减少每位面积和控制体偏置而具有改进的集成度和/或改善性能的非易失性存储器件及其制造方法。非挥发性存储装置可以使用从主体突出的至少一对翅片的外侧表面和/或上表面的表面部分，并且沿着一个方向彼此间隔开，作为至少一对通道地区。可以在沟道区域之间形成至少一个控制栅电极，并且可以在控制栅电极和沟道区域之间的至少一个部分中插入至少一对存储节点。

2. 发明申请

US20070103963A1 Non-volatile memory devices and method thereof 有权
标题翻译：非易失性存储器件及其方法
公开(公告)号：US20070103963A1
公开(公告)日：2007-05-10
申请号：US11490129
申请日：2006-07-21
申请人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
发明人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C16/0416 , G11C2213/31 , G11C2213/32 , G11C2213/72 , H01L27/11521 , H01L27/11568
摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.
摘要翻译：提供了非易失性存储器件及其方法。根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点所述第二存储节点被配置为以第二方式存储信息。根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区，有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向源区域。示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

3. 发明授权

US07436704B2 Non-volatile memory devices and method thereof 有权
标题翻译：非易失性存储器件及其方法
公开(公告)号：US07436704B2
公开(公告)日：2008-10-14
申请号：US11490129
申请日：2006-07-21
申请人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
发明人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
IPC分类号： G11C11/34
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C16/0416 , G11C2213/31 , G11C2213/32 , G11C2213/72 , H01L27/11521 , H01L27/11568
摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.
摘要翻译：提供了非易失性存储器件及其方法。根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点所述第二存储节点被配置为以第二方式存储信息。根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区，有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向源区域。示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

4. 发明申请

US20100041224A1 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100041224A1
公开(公告)日：2010-02-18
申请号：US12588064
申请日：2009-10-02
申请人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
发明人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
IPC分类号： H01L21/28
CPC分类号： H01L27/115 , H01L21/764 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.
摘要翻译：非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制栅电极。

5. 发明申请

US20070284648A1 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070284648A1
公开(公告)日：2007-12-13
申请号：US11723222
申请日：2007-03-19
申请人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
发明人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L21/764 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.
摘要翻译：非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制栅电极。

6. 发明申请

US20070183204A1 NAND-type nonvolatile memory devices having common bit lines and methods of operating the same 审中-公开
标题翻译：具有公共位线的NAND型非易失性存储器件及其操作方法
公开(公告)号：US20070183204A1
公开(公告)日：2007-08-09
申请号：US11657652
申请日：2007-01-25
申请人： Suk-Pil Kim , Won-Joo Kim , Yoon-Dong Park , Jae-Woong Hyun , Jung-Hoon Lee
发明人： Suk-Pil Kim , Won-Joo Kim , Yoon-Dong Park , Jae-Woong Hyun , Jung-Hoon Lee
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C7/18
摘要： A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors, a plurality of unit devices and a source selection transistor. Word lines are respectively connected to control gates of the unit devices in the same rows. A first string selection line and a second string selection line are respectively connected to the gates of the string selection transistors of the first string and the second string. A first source selection line and a second source selection line are respectively connected to the gates of the first string and the second string.
摘要翻译： NAND型非易失性存储器件包括第一串和第二串。第一和第二串中的每一个的端部分别连接到公共位线和公共源极线。第一串和第二串中的每一个具有串选择晶体管，多个单元器件和源极选择晶体管。字线分别连接到相同行中的单元设备的控制栅极。第一串选择线和第二串选择线分别连接到第一串和第二串的串选择晶体管的栅极。第一源选择线和第二源选择线分别连接到第一串和第二串的栅极。

7. 发明授权

US07947590B2 Method of manufacturing a non-volatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07947590B2
公开(公告)日：2011-05-24
申请号：US12588064
申请日：2009-10-02
申请人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
发明人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/115 , H01L21/764 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.
摘要翻译：非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制栅电极。

8. 发明授权

US07622761B2 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07622761B2
公开(公告)日：2009-11-24
申请号：US11723222
申请日：2007-03-19
申请人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
发明人： Yoon-Dong Park , Won-Joo Kim , June-Mo Koo , Suk-Pil Kim , Jae-Woong Hyun , Jung-Hoon Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/764 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792
摘要： The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.
摘要翻译：非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制栅电极。

9. 发明申请

US20060289940A1 Fin FET CMOS device, method of manufacturing the same, and memory including fin FET CMOS device 审中-公开
标题翻译：鳍FET CMOS器件及其制造方法，以及包括鳍式FET CMOS器件的存储器
公开(公告)号：US20060289940A1
公开(公告)日：2006-12-28
申请号：US11475912
申请日：2006-06-28
申请人： Jae-Woong Hyun , Yoon-Dong Park , Won-joo Kim , Sung-jae Byun
发明人： Jae-Woong Hyun , Yoon-Dong Park , Won-joo Kim , Sung-jae Byun
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L27/1211 , H01L29/66795
摘要： A fin FET CMOS device, a method of manufacturing the same, and a memory including the fin FET CMOS device are provided. The CMOS device may include a substrate, an n-type transistor disposed on the substrate, an interlayer insulating layer disposed on the n-type transistor, and a p-type transistor disposed on the interlayer insulating layer. The n-type transistor and the p-type transistor may have a common gate insulating layer and a fin gate.
摘要翻译：提供了翅片FET CMOS器件及其制造方法，以及包括鳍式FET CMOS器件的存储器。 CMOS器件可以包括衬底，设置在衬底上的n型晶体管，设置在n型晶体管上的层间绝缘层和设置在层间绝缘层上的p型晶体管。 n型晶体管和p型晶体管可以具有公共栅绝缘层和鳍栅极。

10. 发明授权

US07514325B2 Fin-FET having GAA structure and methods of fabricating the same 有权
标题翻译：具有GAA结构的Fin-FET及其制造方法
公开(公告)号：US07514325B2
公开(公告)日：2009-04-07
申请号：US11505936
申请日：2006-08-18
申请人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
发明人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795
摘要： Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.
摘要翻译：本发明的示例性实施例涉及一种半导体器件及其制造方法。本发明的其它示例性实施例涉及一种具有鳍型沟道区的鳍式场效应晶体管（Fin-FET）及其制造方法。提供了可以使用围绕鳍片的整个区域作为沟道区域的具有栅极全（GAA）结构的鳍FET。具有GAA结构的Fin-FET包括具有主体，一对支撑柱和鳍的半导体衬底。一对支柱可能从身体突出。翅片可以与主体间隔开，并且可以具有连接到一对支撑柱并由其支撑的端部。栅电极可围绕半导体衬底的鳍的至少一部分。栅电极可以与半导体衬底绝缘。栅极绝缘层可以插入在半导体衬底的栅电极和鳍之间。

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