专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070019479A1 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US20070019479A1
公开(公告)日：2007-01-25
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： G11C7/10
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

2. 发明授权

US07352037B2 Semiconductor device and random access memory having single gate electrode corresponding to a pair of channel regions 有权
标题翻译：具有对应于一对通道区域的单个栅电极的半导体器件和随机存取存储器
公开(公告)号：US07352037B2
公开(公告)日：2008-04-01
申请号：US11393750
申请日：2006-03-31
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , Eun-Hong Lee , Jae-woong Hyun , Jung-hoon Lee , Sung-jae Byun
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/11507 , H01L27/2436 , H01L29/785
摘要： A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.
摘要翻译：半导体器件可以包括半导体衬底上的至少一对散热片。可以在每个鳍中形成沟道区。半导体器件还可以包括对应于每对沟道区的栅电极，同时电连接到形成在相应散热片上的至少一个源中的每一个的源极接触插塞以及电连接到至少一个漏斗同时形成在相应的翅片上。

3. 发明申请

US20070018237A1 Non-volatile memory device having fin-type channel region and method of fabricating the same 审中-公开
标题翻译：具有鳍型沟道区的非易失性存储器件及其制造方法
公开(公告)号：US20070018237A1
公开(公告)日：2007-01-25
申请号：US11489445
申请日：2006-07-20
申请人： Won-Joo Kim , Suk-Pil Kim , Yoon-Dong Park , Eun-Hong Lee , Jae-Woong Hyun , Sung-Jae Byun , Jung-Hoon Lee
发明人： Won-Joo Kim , Suk-Pil Kim , Yoon-Dong Park , Eun-Hong Lee , Jae-Woong Hyun , Sung-Jae Byun , Jung-Hoon Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/7851 , H01L29/792
摘要： A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair of fins protruding from a body and extending, spaced from each other along one direction, as at least one pair of channel regions. At least one control gate electrode may be formed across the channel regions, and at least one pair of storage nodes may be interposed in at least one portion between the control gate electrode and the channel regions.
摘要翻译：具有通过减少每位面积和控制体偏置而具有改进的集成度和/或改善性能的非易失性存储器件及其制造方法。非挥发性存储装置可以使用从主体突出的至少一对翅片的外侧表面和/或上表面的表面部分，并且沿着一个方向彼此间隔开，作为至少一对通道地区。可以在沟道区域之间形成至少一个控制栅电极，并且可以在控制栅电极和沟道区域之间的至少一个部分中插入至少一对存储节点。

4. 发明申请

US20070103963A1 Non-volatile memory devices and method thereof 有权
标题翻译：非易失性存储器件及其方法
公开(公告)号：US20070103963A1
公开(公告)日：2007-05-10
申请号：US11490129
申请日：2006-07-21
申请人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
发明人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C16/0416 , G11C2213/31 , G11C2213/32 , G11C2213/72 , H01L27/11521 , H01L27/11568
摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.
摘要翻译：提供了非易失性存储器件及其方法。根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点所述第二存储节点被配置为以第二方式存储信息。根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区，有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向源区域。示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

5. 发明授权

US07436704B2 Non-volatile memory devices and method thereof 有权
标题翻译：非易失性存储器件及其方法
公开(公告)号：US07436704B2
公开(公告)日：2008-10-14
申请号：US11490129
申请日：2006-07-21
申请人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
发明人： Won-Joo Kim , Sung-Jae Byun , Yoon-Dong Park , Eun-Hong Lee , Suk-Pil Kim , Jae-Woong Hyun
IPC分类号： G11C11/34
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C16/0416 , G11C2213/31 , G11C2213/32 , G11C2213/72 , H01L27/11521 , H01L27/11568
摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.
摘要翻译：提供了非易失性存储器件及其方法。根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点所述第二存储节点被配置为以第二方式存储信息。根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区，有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向源区域。示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

6. 发明授权

US08455854B2 Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same 有权
标题翻译：包括非晶合金金属氧化物层的非易失性存储器件及其制造方法
公开(公告)号：US08455854B2
公开(公告)日：2013-06-04
申请号：US11704365
申请日：2007-02-09
申请人： Choong-Rae Cho , Sung-Il Cho , In-Kyeong Yoo , Eun-Hong Lee , Chang-Wook Moon
发明人： Choong-Rae Cho , Sung-Il Cho , In-Kyeong Yoo , Eun-Hong Lee , Chang-Wook Moon
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L21/31691 , H01L29/47 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.
摘要翻译：非易失性存储器件可以包括下电极，包括设置在下电极上的非晶合金金属氧化物的氧化物层和设置在氧化物层上的二极管结构。

7. 发明授权

US08350262B2 Nonvolatile memory device and nonvolatile memory array including the same 有权
标题翻译：非易失性存储器件和包括其的非易失性存储器阵列
公开(公告)号：US08350262B2
公开(公告)日：2013-01-08
申请号：US12929121
申请日：2011-01-03
申请人： Myoung-Jae Lee , In-Kyeong Yoo , Eun-Hong Lee , Jong-Wan Kim , Dong-Chul Kim , Seung-Eon Ahn
发明人： Myoung-Jae Lee , In-Kyeong Yoo , Eun-Hong Lee , Jong-Wan Kim , Dong-Chul Kim , Seung-Eon Ahn
IPC分类号： H01L29/10 , H01L29/12
CPC分类号： H01L27/1021 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/73
摘要： A nonvolatile memory device having self-presence diode characteristics, and/or a nonvolatile memory array including the nonvolatile memory device may be provided. The nonvolatile memory device may include a lower electrode, a first semiconductor oxide layer on the lower electrode, a second semiconductor oxide layer on the first semiconductor oxide layer, and/or an upper electrode on the second semiconductor oxide layer.
摘要翻译：可以提供具有自身存在二极管特性的非易失性存储器件和/或包括非易失性存储器件的非易失性存储器阵列。非易失性存储器件可以包括下电极，下电极上的第一半导体氧化物层，第一半导体氧化物层上的第二半导体氧化物层，和/或第二半导体氧化物层上的上电极。

8. 发明申请

US20070295950A1 Variable resistance random access memory device and a method of fabricating the same 有权
标题翻译：可变电阻随机存取存储器件及其制造方法
公开(公告)号：US20070295950A1
公开(公告)日：2007-12-27
申请号：US11702623
申请日：2007-02-06
申请人： Choong-Rae Cho , Eun-Hong Lee , Stefanovich Genrikh , El Mostafa Bourim
发明人： Choong-Rae Cho , Eun-Hong Lee , Stefanovich Genrikh , El Mostafa Bourim
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146 , Y10S438/90
摘要： Provided is a variable resistance random access memory device having an n+ interfacial layer and a method of fabricating the same. The variable resistance random access memory device may include a lower electrode, an n+ interfacial layer on the lower electrode, a buffer layer on the n+ interfacial layer, an oxide layer on the buffer layer and having a variable resistance characteristic and an upper electrode on the oxide layer.
摘要翻译：提供了具有n +界面层的可变电阻随机存取存储器件及其制造方法。可变电阻随机存取存储器件可以包括下电极，下电极上的n +界面层，n +界面层上的缓冲层，缓冲层上的氧化物层和可变电阻特性上的上电极氧化层。

9. 发明申请

US20070252193A1 Non-volatile memory devices including variable resistance material 有权
标题翻译：包括可变电阻材料的非易失性存储器件
公开(公告)号：US20070252193A1
公开(公告)日：2007-11-01
申请号：US11785478
申请日：2007-04-18
申请人： Choong-Rae Cho , Eun-Hong Lee , El Mostafa Bourim , Chang-Wook Moon
发明人： Choong-Rae Cho , Eun-Hong Lee , El Mostafa Bourim , Chang-Wook Moon
IPC分类号： H01L29/788
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/52 , H01L29/24 , H01L29/8615 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile memory device comprises a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an alloy thereof, the second oxide layer is a transition metal oxide, the buffer layer is composed of a p-type oxide and the upper electrode is composed of a material selected from Ni, Co, Cr, W, Cu or an alloy thereof.
摘要翻译：非易失性存储器件包括形成在下电极上的第一氧化物层，第二氧化物层和缓冲层。在缓冲层上形成上电极。在一个示例中，下电极由Pt，Ru，Ir，IrOx及其合金中的至少一种构成，第二氧化物层是过渡金属氧化物，缓冲层由p型氧化物和上部电极由选自Ni，Co，Cr，W，Cu或其合金的材料构成。

10. 发明申请

US20070189065A1 Phase-change random access memory and programming method 有权
标题翻译：相变随机存取存储器和编程方法
公开(公告)号：US20070189065A1
公开(公告)日：2007-08-16
申请号：US11657649
申请日：2007-01-25
申请人： Dong-Seok Suh , Eun-Hong Lee , Jin-Seo Noh
发明人： Dong-Seok Suh , Eun-Hong Lee , Jin-Seo Noh
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/77
摘要： A programming method for a phase-change random access memory (PRAM) may be provided. The programming method may include determining an amorphous state of a chalcogenide material using programming pulses to form programming areas having threshold voltages corresponding to logic high and logic low, and/or controlling a trailing edge of programming pulses during programming to control a quenching speed of the chalcogenide material so as to adjust a threshold voltage of the chalcogenide material. Accordingly, programming pulses corresponding to logic low or logic high may have uniform magnitudes regardless of a corresponding logic level. Accordingly, reliability of a PRAM device may be improved.
摘要翻译：可以提供用于相变随机存取存储器（PRAM）的编程方法。编程方法可以包括使用编程脉冲来确定硫族化物材料的非晶状态，以形成具有对应于逻辑高和逻辑低的阈值电压的编程区域，和/或在编程期间控制编程脉冲的后沿以控制编程脉冲的淬灭速度硫属化物材料，以便调节硫族化物材料的阈值电压。因此，对应于逻辑低或逻辑高的编程脉冲可以具有均匀的幅度，而与对应的逻辑电平无关。因此，可以提高PRAM装置的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式