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1. 发明申请

US20100276756A1 SUBSTRATE FINS WITH DIFFERENT HEIGHTS 有权
标题翻译：带不同高度的基座
公开(公告)号：US20100276756A1
公开(公告)日：2010-11-04
申请号：US12837321
申请日：2010-07-15
申请人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
发明人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/76 , H01L21/76232 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
摘要翻译：一种装置包括多个翅片。一些翅片比其他翅片具有更高的高度。这允许选择不同的驱动电流和/或晶体管区域。

2. 发明授权

US08441074B2 Substrate fins with different heights 有权
公开(公告)号：US08441074B2
公开(公告)日：2013-05-14
申请号：US12837321
申请日：2010-07-15
申请人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
发明人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
IPC分类号： H01L29/66
CPC分类号： H01L21/76 , H01L21/76232 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.

3. 发明授权

US08629039B2 Substrate fins with different heights 有权
标题翻译：不同高度的基片
公开(公告)号：US08629039B2
公开(公告)日：2014-01-14
申请号：US13875412
申请日：2013-05-02
申请人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
发明人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
IPC分类号： H01L21/76
CPC分类号： H01L21/76 , H01L21/76232 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
摘要翻译：一种装置包括多个翅片。一些翅片比其他翅片具有更高的高度。这允许选择不同的驱动电流和/或晶体管区域。

4. 发明申请

US20130273710A1 SUBSTRATE FINS WITH DIFFERENT HEIGHTS 有权
标题翻译：带不同高度的基座
公开(公告)号：US20130273710A1
公开(公告)日：2013-10-17
申请号：US13875412
申请日：2013-05-02
申请人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
发明人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
IPC分类号： H01L21/76
CPC分类号： H01L21/76 , H01L21/76232 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
摘要翻译：一种装置包括多个翅片。一些翅片比其他翅片具有更高的高度。这允许选择不同的驱动电流和/或晶体管区域。

5. 发明申请

US20090321834A1 Substrate fins with different heights 审中-公开
标题翻译：不同高度的基片
公开(公告)号：US20090321834A1
公开(公告)日：2009-12-31
申请号：US12215778
申请日：2008-06-30
申请人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
发明人： Willy Rachmady , Justin S. Sandford , Michael K. Harper
IPC分类号： H01L21/762 , H01L27/088
CPC分类号： H01L21/76 , H01L21/76232 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.
摘要翻译：一种装置包括多个翅片。一些翅片比其他翅片具有更高的高度。这允许选择不同的驱动电流和/或晶体管区域。

6. 发明申请

US20090079014A1 TRANSISTORS WITH HIGH-K DIELECTRIC SPACER LINER TO MITIGATE LATERAL OXIDE ENCROACHMENT 有权
标题翻译：具有高K电介质间隔器的晶体管，用于减缓侧面氧化物的侵蚀
公开(公告)号：US20090079014A1
公开(公告)日：2009-03-26
申请号：US11862017
申请日：2007-09-26
申请人： Justin S. Sandford , Willy Rachmady
发明人： Justin S. Sandford , Willy Rachmady
IPC分类号： H01L29/00
CPC分类号： H01L29/4983 , H01L29/4958 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/78 , Y10S257/90
摘要： Embodiments of the invention generally relate to transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment. In this regard a semiconductor device is introduced having a substrate, a high-k gate dielectric layer on the substrate, a metal gate electrode on the high-k gate dielectric layer, and a high-k dielectric layer on either side of and adjacent to the metal gate electrode and high-k gate dielectric layer, extending a distance away from the metal gate electrode and high-k gate dielectric layer on the substrate. Other embodiments are also disclosed and claimed.
摘要翻译：本发明的实施例通常涉及具有高k电介质隔离衬垫以减轻横向氧化物侵蚀的晶体管。在这方面，引入半导体器件，其具有衬底，衬底上的高k栅极电介质层，高k栅极电介质层上的金属栅极电极，以及高k栅极电介质层上的高k电介质层金属栅极电极和高k栅极电介质层，延伸离开衬底上的金属栅极电极和高k栅极电介质层的距离。还公开并要求保护其他实施例。

7. 发明申请

US20090283922A1 INTEGRATING HIGH STRESS CAP LAYER IN HIGH-K METAL GATE TRANSISTOR 审中-公开
标题翻译：在高K金属栅极晶体管中集成高应力CAP层
公开(公告)号：US20090283922A1
公开(公告)日：2009-11-19
申请号：US11965317
申请日：2007-12-27
申请人： Willy Rachmady , Justin S. Sandford , Oleg Golonzka
发明人： Willy Rachmady , Justin S. Sandford , Oleg Golonzka
IPC分类号： H01L21/311 , H01L23/29
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/31111 , H01L29/4966 , H01L29/7847
摘要： In some embodiments an etchstop layer is deposited over a transistor that has been encapsulated by a high-K film, a silicon nitride is deposited over the deposited etchstop layer, the silicon nitride is removed, and the etchstop layer is removed. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，蚀刻阻挡层沉积在已经被高K膜封装的晶体管上，氮化硅沉积在沉积的蚀刻阻挡层上，氮化硅被去除，并且蚀刻阻挡层被去除。描述和要求保护其他实施例。

8. 发明授权

US07768079B2 Transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachement 有权
标题翻译：具有高k介电隔离衬垫的晶体管，以减轻横向氧化物侵蚀
公开(公告)号：US07768079B2
公开(公告)日：2010-08-03
申请号：US11862017
申请日：2007-09-26
申请人： Justin S. Sandford , Willy Rachmady
发明人： Justin S. Sandford , Willy Rachmady
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L29/4958 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/78 , Y10S257/90
摘要： Embodiments of the invention generally relate to transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment. In this regard a semiconductor device is introduced having a substrate, a high-k gate dielectric layer on the substrate, a metal gate electrode on the high-k gate dielectric layer, and a high-k dielectric layer on either side of and adjacent to the metal gate electrode and high-k gate dielectric layer, extending a distance away from the metal gate electrode and high-k gate dielectric layer on the substrate. Other embodiments are also disclosed and claimed.
摘要翻译：本发明的实施例通常涉及具有高k电介质隔离衬垫以减轻横向氧化物侵蚀的晶体管。在这方面，引入半导体器件，其具有衬底，衬底上的高k栅极电介质层，高k栅极电介质层上的金属栅极电极，以及高k栅极电介质层上的高k电介质层金属栅极电极和高k栅极电介质层，延伸离开衬底上的金属栅极电极和高k栅极电介质层的距离。还公开并要求保护其他实施例。

9. 发明申请

US20090057788A1 Angled implantation for removal of thin film layers 审中-公开
公开(公告)号：US20090057788A1
公开(公告)日：2009-03-05
申请号：US12288944
申请日：2008-10-24
申请人： Michael L. Hattendorf , Justin K. Brask , Justin S. Sandford , Jack Kavalieros , Matthew V. Metz
发明人： Michael L. Hattendorf , Justin K. Brask , Justin S. Sandford , Jack Kavalieros , Matthew V. Metz
IPC分类号： H01L29/78
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L21/32136 , H01L21/32137 , H01L29/42376 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

10. 发明授权

US06362034B1 Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field 有权
标题翻译：形成具有降低的耗尽区生长灵敏度的施加电场的MOSFET栅电极的方法
公开(公告)号：US06362034B1
公开(公告)日：2002-03-26
申请号：US09471815
申请日：1999-12-20
申请人： Justin S. Sandford , Kaizad R. Mistry
发明人： Justin S. Sandford , Kaizad R. Mistry
IPC分类号： H01L21336
CPC分类号： H01L21/823842 , H01L21/823814
摘要： A method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an n-channel FET. In one embodiment of the present invention, an integrated circuit including NFETs and PFETs is produced with increased n-type doping in the n-channel FET gate electrodes without the use of additional photomasking operations. Prior to polysilicon patterning, a phosphorus doped silica glass (PSG) is deposited over the polysilicon. Subsequent to patterning of the polysilicon, NFET areas are masked, and exposed PFET areas subjected to source/drain extension implant operations. During this sequence, the PSG is removed from PFET areas but remains in the NFET areas. An anneal is performed to drive the phosphorus from the PSG into the NFET gate electrodes. NFET source/drain extensions are formed, and conventional MOSFET processing operations may then be performed to complete the integrated circuit. Embodiments of the present invention achieve the desired higher levels of doping without an additional masking operation, thereby achieving the desired electrical characteristics at a lower manufacturing cost.
摘要翻译：制造具有对载流子耗尽效应的敏感性降低的栅电极的FET的方法包括增加n沟道FET的栅电极中的n型掺杂剂的量。在本发明的一个实施例中，在不使用额外的光掩模操作的情况下，在n沟道FET栅电极中产生具有增加的n型掺杂的NFET和PFET的集成电路。在多晶硅图案化之前，在多晶硅上沉积磷掺杂石英玻璃（PSG）。在多晶硅的图案化之后，NFET区域被掩蔽，并且暴露的PFET区域经受源极/漏极延伸注入操作。在该序列期间，PSG从PFET区域移除，但仍保留在NFET区域中。执行退火以将磷从PSG驱动到NFET栅电极中。形成NFET源极/漏极延伸部，然后可以执行常规的MOSFET处理操作来完成集成电路。本发明的实施例在没有额外的掩蔽操作的情况下实现期望的更高水平的掺杂，从而以较低的制造成本实现期望的电特性。

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