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1. 发明授权

US07319348B2 Circuits for locally generating non-integral divided clocks with centralized state machines 失效
标题翻译：用集中式状态机本地生成非积分分时钟的电路
公开(公告)号：US07319348B2
公开(公告)日：2008-01-15
申请号：US11341032
申请日：2006-01-27
申请人： William V. Huott , Charlie C. Hwang , Timothy C. McNamara
发明人： William V. Huott , Charlie C. Hwang , Timothy C. McNamara
IPC分类号： G06F1/04
CPC分类号： H03K23/502
摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译：本地生成芯片上的比率时钟的电路。该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。状态机包括响应于非整数个全局时钟周期的整个周期的计数器。状态机响应于计数器产生控制信号。分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有符合目标分频时钟频率和占空比的模式。本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。

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