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1. 发明申请

WO2009089321A2 DIGITAL FEEQUENCY GENERATOR 审中-公开
标题翻译：数字式发电机
公开(公告)号：WO2009089321A2
公开(公告)日：2009-07-16
申请号：PCT/US2009/030398
申请日：2009-01-08
申请人： ESS TECHNOLOGY, INC. , MALLINSON, Andrew, Martin
发明人： MALLINSON, Andrew, Martin
CPC分类号： H03K3/0315 , H03K23/004 , H03K23/502 , H03L1/00 , H03L1/027
摘要： Discussed herein are a feed-forward control loop, 'almost-binary' counter, and ring oscillator.
摘要翻译：这里讨论的是前馈控制回路，“几何二进制”计数器和环形振荡器。

2. 发明申请

WO2009089321A3 DIGITAL FEEQUENCY GENERATOR 审中-公开
标题翻译：数字式发电机
公开(公告)号：WO2009089321A3
公开(公告)日：2009-12-03
申请号：PCT/US2009030398
申请日：2009-01-08
申请人： ESS TECHNOLOGY INC , MALLINSON ANDREW MARTIN
发明人： MALLINSON ANDREW MARTIN
IPC分类号： H03B28/00
CPC分类号： H03K3/0315 , H03K23/004 , H03K23/502 , H03L1/00 , H03L1/027
摘要： A feed-forward control loop circuit, almost-binary counter and ring oscillator, comprising: an oscillation source; a reference frequency source having a second frequency independently generated from the oscillation source; a measurement circuit responsive to the reference source and the oscillation source; a first circuit accepting an input frequency and creating an output frequency dependent on another input; and a second circuit operating on an output of the measurement circuit and receiving a frequency input. The feed-forward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward control loop.
摘要翻译：一种前馈控制回路电路，几乎是二进制计数器和环形振荡器，包括：振荡源; 具有从振荡源独立产生的第二频率的参考频率源; 响应于参考源和振荡源的测量电路; 第一电路接受输入频率并产生取决于另一输入的输出频率; 以及在所述测量电路的输出上工作并接收频率输入的第二电路。前馈控制环路产生来自第一电路的输出，参考源和频率输入足以确定前馈控制回路的输出。

3. 发明申请

WO2009089321A4 DIGITAL FEEQUENCY GENERATOR 审中-公开
标题翻译：数字式发电机
公开(公告)号：WO2009089321A4
公开(公告)日：2010-02-25
申请号：PCT/US2009030398
申请日：2009-01-08
申请人： ESS TECHNOLOGY INC , MALLINSON ANDREW MARTIN
发明人： MALLINSON ANDREW MARTIN
IPC分类号： H03B28/00
CPC分类号： H03K3/0315 , H03K23/004 , H03K23/502 , H03L1/00 , H03L1/027
摘要： A feed-forward control loop circuit, almost-binary counter and ring oscillator, comprising: an oscillation source; a reference frequency source having a second frequency independently generated from the oscillation source; a measurement circuit responsive to the reference source and the oscillation source; a first circuit accepting an input frequency and creating an output frequency dependent on another input; and a second circuit operating on an output of the measurement circuit and receiving a frequency input. The feed-forward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward control loop.
摘要翻译：一种前馈控制回路电路，几乎是二进制计数器和环形振荡器，包括：振荡源; 具有从振荡源独立产生的第二频率的参考频率源; 响应于参考源和振荡源的测量电路; 第一电路接受输入频率并产生取决于另一输入的输出频率; 以及在所述测量电路的输出上工作并接收频率输入的第二电路。前馈控制环路产生来自第一电路的输出，参考源和频率输入足以确定前馈控制回路的输出。

4. 实用新型

JPS6114203Y2 JPS6114203Y2 - 失效
公开(公告)号：JPS6114203Y2
公开(公告)日：1986-05-02
申请号：JP19325084
申请日：1984-12-20
IPC分类号： H03K21/00 , G11C19/28 , H03K23/50 , H03K23/66 , H03K23/54 , H03K23/40
CPC分类号： G11C19/28 , H03K23/502 , H03K23/665

5. 发明专利

JP2017022490A デジタル制御発振回路审中-公开
标题翻译：数控振荡器电路
公开(公告)号：JP2017022490A
公开(公告)日：2017-01-26
申请号：JP2015137103
申请日：2015-07-08
申请人：株式会社デンソー
发明人：山内重徳 , 田口信幸 , 渡辺高元
IPC分类号： H03K5/00 , H03L7/06
CPC分类号： H03L7/0997 , G04F10/005 , G06F1/12 , H03K23/425 , H03K23/502 , H03K3/0315 , H03K5/135 , H03L7/091 , H03L7/1974
摘要：【課題】周期の長さによらず精度の安定したクロックを生成する技術を提供する。【解決手段】粗周期生成部(71)は、予め用意された基準クロックの周期に対する倍率で表された周期設定値を取得し、倍率の整数部をカウント値として、基準クロックをカウントとすることで、整数部が表す周期毎の粗周期タイミングを生成する。端数換算部(72)は、倍率の小数点部を、パルス信号が遅延素子を通過する段数に換算することで端数を生成する。出力処理部(73,8)は、リングオシレータおよびカウンタ回路の出力が、換算部で生成された端数に対応した値となるタイミングを、粗周期タイミングから端数に対応した時間だけ経過した出力タイミングとして選択し、該出力タイミングを用いて周期設定値が示す周期で発振する出力信号を生成する。【選択図】図16
摘要翻译：为不管期间的长度来生成精度稳定的时钟的技术。粗周期产生单元（71）获取表示作为基准时钟被预先准备，所述比率作为计数值的整数部分的周期的比例的周期设定值，对基准时钟的计数在，它产生的整数部分表示每个循环的周期粗定时。分数转换单元（72），放大倍率的小数部分，一个脉冲信号，以通过转换的通过延迟元件的步数产生一小部分。输出处理单元（73,8），环形振荡器和计数器电路的输出，在其中对应于由所述转换单元产生的分数的值的定时，作为输出定时已经通过从粗周期定时对应于该级分中的时间经过的选择时，它产生与通过利用输出的定时为止的期间设定值所指示的周期振荡的输出信号。 .The 16

6. 发明专利

JP2009201037A Frequency divider circuit 有权
标题翻译：频率分路电路
公开(公告)号：JP2009201037A
公开(公告)日：2009-09-03
申请号：JP2008043132
申请日：2008-02-25
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： MITSUISHI MASASHI
IPC分类号： H03K23/64
CPC分类号： H03K23/502 , H03K23/667 , H03K23/68
摘要： PROBLEM TO BE SOLVED: To implement a self-recovery type or reset-free type 6-, 7-, and 8-frequency division switching circuit that has a small number of elements and reduces a circuit area and power consumption.
SOLUTION: The circuit comprises edge-trigger type FFs (flip-flops) 101-105 having a common input of a clock signal, an output of the FF 101 connected to an input of the FF 102. It comprises: a logic gate 106 outputting an output of the FF 102 when a control signal D67 is active and outputting a predetermined fixed value when the control signal D67 is inactive; and a logic gate 107 outputting an output of the FF 101 when the control signal D78 is active and outputting a predetermined fixed value when the control signal D78 is inactive. The FF103 receives an output of the logic gate 106 as input, the logic gate 108 receives the outputs of the FF 103 and FF 105 as input, the FF 104 receives an output of the logic gate 108 as input to feed back an output of the FF 104 to the FF 101.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：实现具有少量元件并减少电路面积和功耗的自恢复型或无复位型6-，7-和8-分频开关电路。解决方案：电路包括具有时钟信号的公共输入的边沿触发型FF（触发器）101-105，连接到FF 102的输入的FF 101的输出。它包括：逻辑当控制信号D67有效时，门106输出FF102的输出，并且当控制信号D67无效时输出预定的固定值; 以及逻辑门107，当控制信号D78有效时输出FF101的输出，并且当控制信号D78不活动时输出预定的固定值。 FF103接收逻辑门106的输出作为输入，逻辑门108接收FF 103和FF 105的输出作为输入，FF 104接收逻辑门108的输出作为输入，以反馈输出 FF 104到FF 101.版权所有（C）2009，JPO＆INPIT

7. 发明申请

US20180367129A1 FOLDED DIVIDER ARCHITECTURE 审中-公开
公开(公告)号：US20180367129A1
公开(公告)日：2018-12-20
申请号：US16113235
申请日：2018-08-27
申请人： STMicroelectronics Asia Pacific Pte Ltd
发明人： Beng-Heng Goh
IPC分类号： H03K5/15 , H03L7/16 , H03K23/50 , H03L7/183 , H03L7/197
CPC分类号： H03K5/15033 , H03K23/502 , H03L7/16 , H03L7/183 , H03L7/1974
摘要： A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.

8. 发明授权

US09667262B2 Digital control oscillator circuit 有权
公开(公告)号：US09667262B2
公开(公告)日：2017-05-30
申请号：US15189017
申请日：2016-06-22
申请人： DENSO CORPORATION
发明人： Shigenori Yamauchi , Nobuyuki Taguchi , Takamoto Watanabe
IPC分类号： H03K3/03 , H03L7/099 , H03L7/091 , H03L7/197 , H03K23/50 , G06F1/12 , H03K23/42 , H03K5/135 , G04F10/00
CPC分类号： H03L7/0997 , G04F10/005 , G06F1/12 , H03K3/0315 , H03K5/135 , H03K23/425 , H03K23/502 , H03L7/091 , H03L7/1974
摘要： A digital control oscillator circuit includes: a ring oscillator having delay elements delaying a pulse signal; a counter circuit counting the circulation number of the pulse signal; a rough period generation unit acquiring a period setting value as a magnification ratio for a reference clock, and counting the reference clock using an integer part of the ratio to generate a rough period timing; a fraction conversion unit converting a decimal point part of the ratio into the number of the elements passed by the pulse signal to generate a fraction; and an output processing unit selecting a timing when outputs of the ring oscillator and the counter circuit become values corresponding to the fraction as an output timing when a time corresponding to the fraction has passed after the rough period timing, and generating an output signal oscillating at a period represented by the period setting value according to the output timing.

9. 发明授权

US07319348B2 Circuits for locally generating non-integral divided clocks with centralized state machines 失效
标题翻译：用集中式状态机本地生成非积分分时钟的电路
公开(公告)号：US07319348B2
公开(公告)日：2008-01-15
申请号：US11341032
申请日：2006-01-27
申请人： William V. Huott , Charlie C. Hwang , Timothy C. McNamara
发明人： William V. Huott , Charlie C. Hwang , Timothy C. McNamara
IPC分类号： G06F1/04
CPC分类号： H03K23/502
摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译：本地生成芯片上的比率时钟的电路。该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。状态机包括响应于非整数个全局时钟周期的整个周期的计数器。状态机响应于计数器产生控制信号。分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有符合目标分频时钟频率和占空比的模式。本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。

10. 发明授权

US3377469A Electronic counting apparatus 失效
标题翻译：电子计数器
公开(公告)号：US3377469A
公开(公告)日：1968-04-09
申请号：US39445564
申请日：1964-09-04
申请人： BERTRAM D. SOLOMON
发明人： SOLOMON BERTRAM D
IPC分类号： H03K23/50
CPC分类号： H03K23/502

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