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1. 发明授权

US07016826B2 Apparatus and method of developing software for a multi-processor chip 失效
公开(公告)号：US07016826B2
公开(公告)日：2006-03-21
申请号：US09745561
申请日：2000-12-21
申请人： William R. Wheeler , Lai-Wah Hui , Donald F. Hooper , Serge Kornfeld , James D. Guilford
发明人： William R. Wheeler , Lai-Wah Hui , Donald F. Hooper , Serge Kornfeld , James D. Guilford
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.

2. 发明授权

US07020871B2 Breakpoint method for parallel hardware threads in multithreaded processor 失效
标题翻译：多线程处理器中并行硬件线程的断点方法
公开(公告)号：US07020871B2
公开(公告)日：2006-03-28
申请号：US09747019
申请日：2000-12-21
申请人： Debra Bernstein , Serge Kornfeld , Desmond R. Johnson , Donald F. Hooper , James D. Guilford , Richard D. Muratori
发明人： Debra Bernstein , Serge Kornfeld , Desmond R. Johnson , Donald F. Hooper , James D. Guilford , Richard D. Muratori
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.
摘要翻译：调试在具有微引擎的多线程处理器中执行的代码的方法包括从连接到处理器的远程用户界面接收表示所选择的一个微引擎中的所选择的一个微指令的标识，所述远程用户界面暂停在所选择的微引擎中执行的线程中的程序执行，在所选择的微引擎中的程序指令之后插入与从远程用户界面接收的程序指令相匹配的断点，恢复所选微引擎中的程序执行，执行断点程序，如果所选择的微引擎中的程序执行遇到断点并恢复程序执行微型发动机。

3. 发明授权

US06684395B2 Multiple image dynamic bind and load procedure for a multi-processor 失效
标题翻译：多处理器的多图像动态绑定和加载过程
公开(公告)号：US06684395B2
公开(公告)日：2004-01-27
申请号：US09753084
申请日：2000-12-28
申请人： Desmond R. Johnson , Donald F. Hooper , James D. Guilford
发明人： Desmond R. Johnson , Donald F. Hooper , James D. Guilford
IPC分类号： G06F944
CPC分类号： G06F9/44521
摘要： A method and mechanism for executing an application by a processor in a multi-processor configuration of processors, each having an associated instruction memory is presented. The application receives object code that includes an image for at least one other processor in the multi-processor configuration of processors. The application binds an import variable in the image to a parameter value and stores the image for the at least one other processor into the associated instruction memory.
摘要翻译：提出了一种用于在处理器的多处理器配置中由处理器执行应用的方法和机制，每个处理器具有相关联的指令存储器。该应用接收处理器的多处理器配置中的至少一个其他处理器的图像的目标代码。应用程序将图像中的导入变量绑定到参数值，并将至少一个其他处理器的映像存储到相关联的指令存储器中。

4. 发明授权

US06944850B2 Hop method for stepping parallel hardware threads 失效
标题翻译：用于并行硬件线程的Hop方法
公开(公告)号：US06944850B2
公开(公告)日：2005-09-13
申请号：US09746523
申请日：2000-12-21
申请人： Donald F. Hooper , Desmond R. Johnson , James D. Guilford , Richard D. Muratori
发明人： Donald F. Hooper , Desmond R. Johnson , James D. Guilford , Richard D. Muratori
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F11/3644 , G06F9/3824 , G06F9/3851 , G06F9/3861
摘要： A method of debugging software that executes in a multithreaded processor having a plurality of microengines includes pausing program execution in threads of execution within a target microengine, inserting a segment of executable code into an unused section of the target microengine's microstore, executing the segment of executable code in the target microengine and resuming program execution in the target microengine
摘要翻译：调试在具有多个微引擎的多线程处理器中执行的软件的方法包括在目标微引擎内暂停执行线程中的程序执行，将一段可执行代码插入到目标微引擎的微型存储器的未使用部分中，执行可执行程序段目标微引擎中的代码，并恢复目标微引擎中的程序执行

5. 发明授权

US06671827B2 Journaling for parallel hardware threads in multithreaded processor 失效
公开(公告)号：US06671827B2
公开(公告)日：2003-12-30
申请号：US09747018
申请日：2000-12-21
申请人： James D. Guilford , William R. Wheeler , Matthew J. Adiletta , Daniel Cutter
发明人： James D. Guilford , William R. Wheeler , Matthew J. Adiletta , Daniel Cutter
IPC分类号： F11
CPC分类号： G06F11/3636
摘要： A method of debugging code that executes in a multithreaded processor having microengines includes receiving a journal write command and an identification representing a selected one of the microengines from a remote user interface connected to the processor, pausing program execution in the threads executing in the selected microengine, inserting a journal write command at a current program counter in the selected microengine, resuming program execution in the selected microengine, executing a write to a journal routine if program execution in the selected microengine encounters the journal write command and resuming program execution in the microengine.

6. 发明申请

US20180095760A1 INSTRUCTION SET FOR VARIABLE LENGTH INTEGER CODING 审中-公开
公开(公告)号：US20180095760A1
公开(公告)日：2018-04-05
申请号：US15281380
申请日：2016-09-30
申请人： James D. Guilford , Vinodh Gopal
发明人： James D. Guilford , Vinodh Gopal
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30018 , G06F9/30025 , G06F9/30192
摘要： Instruction sets for variable length integer (varint) coding and associated methods and apparatus. The instructions sets include instructions for encoding and decoding varints, and may be included as a part of an instruction set architecture (ISA) for processors architectures such as x86 and Arm-based architectures, as well as other ISAs. In one aspect, the instructions include, a varint size encode instruction to encode a size of a varint, a varint encode instruction to encode a varint, a varint size decode instruction to decode a size of an encoded varint, and a varint decode instruction to decode an encoded varint. Varint encode size and encode instructions may be combined in a single instructions. Similarly, varint decode size and decode instructions may be combined in a single instruction. In one aspect, the instructions use a variable-length quantity (VLQ) encoding scheme under which varints are encoded into one or more VLQ octets.

7. 发明授权

US09632782B2 Method and apparatus to process SHA-2 secure hashing algorithm 有权
公开(公告)号：US09632782B2
公开(公告)日：2017-04-25
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , G06F21/60 , H04L9/06 , H04L9/32
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

8. 发明授权

US09292548B2 Digest generation 有权
标题翻译：消化一代
公开(公告)号：US09292548B2
公开(公告)日：2016-03-22
申请号：US13995236
申请日：2011-11-01
申请人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
发明人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30306 , G06F17/3033
摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
摘要翻译：在一个实施例中，电路可以生成待组合的摘要以产生散列值。摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

9. 发明授权

US09092645B2 Efficient multiplication, exponentiation and modular reduction implementations 有权
标题翻译：有效的乘法，乘法和模块化削减实现
公开(公告)号：US09092645B2
公开(公告)日：2015-07-28
申请号：US13994782
申请日：2011-12-05
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： H04L29/00 , G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

10. 发明申请

US20150082047A1 EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
标题翻译：有效的实施，授权和模块化的减少实施
公开(公告)号：US20150082047A1
公开(公告)日：2015-03-19
申请号：US13994782
申请日：2011-12-05
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

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