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1. 发明授权

US07020871B2 Breakpoint method for parallel hardware threads in multithreaded processor 失效
标题翻译：多线程处理器中并行硬件线程的断点方法
公开(公告)号：US07020871B2
公开(公告)日：2006-03-28
申请号：US09747019
申请日：2000-12-21
申请人： Debra Bernstein , Serge Kornfeld , Desmond R. Johnson , Donald F. Hooper , James D. Guilford , Richard D. Muratori
发明人： Debra Bernstein , Serge Kornfeld , Desmond R. Johnson , Donald F. Hooper , James D. Guilford , Richard D. Muratori
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.
摘要翻译：调试在具有微引擎的多线程处理器中执行的代码的方法包括从连接到处理器的远程用户界面接收表示所选择的一个微引擎中的所选择的一个微指令的标识，所述远程用户界面暂停在所选择的微引擎中执行的线程中的程序执行，在所选择的微引擎中的程序指令之后插入与从远程用户界面接收的程序指令相匹配的断点，恢复所选微引擎中的程序执行，执行断点程序，如果所选择的微引擎中的程序执行遇到断点并恢复程序执行微型发动机。

2. 发明授权

US06944850B2 Hop method for stepping parallel hardware threads 失效
标题翻译：用于并行硬件线程的Hop方法
公开(公告)号：US06944850B2
公开(公告)日：2005-09-13
申请号：US09746523
申请日：2000-12-21
申请人： Donald F. Hooper , Desmond R. Johnson , James D. Guilford , Richard D. Muratori
发明人： Donald F. Hooper , Desmond R. Johnson , James D. Guilford , Richard D. Muratori
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F11/3644 , G06F9/3824 , G06F9/3851 , G06F9/3861
摘要： A method of debugging software that executes in a multithreaded processor having a plurality of microengines includes pausing program execution in threads of execution within a target microengine, inserting a segment of executable code into an unused section of the target microengine's microstore, executing the segment of executable code in the target microengine and resuming program execution in the target microengine
摘要翻译：调试在具有多个微引擎的多线程处理器中执行的软件的方法包括在目标微引擎内暂停执行线程中的程序执行，将一段可执行代码插入到目标微引擎的微型存储器的未使用部分中，执行可执行程序段目标微引擎中的代码，并恢复目标微引擎中的程序执行

3. 发明授权

US07016826B2 Apparatus and method of developing software for a multi-processor chip 失效
公开(公告)号：US07016826B2
公开(公告)日：2006-03-21
申请号：US09745561
申请日：2000-12-21
申请人： William R. Wheeler , Lai-Wah Hui , Donald F. Hooper , Serge Kornfeld , James D. Guilford
发明人： William R. Wheeler , Lai-Wah Hui , Donald F. Hooper , Serge Kornfeld , James D. Guilford
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.

4. 发明授权

US06684395B2 Multiple image dynamic bind and load procedure for a multi-processor 失效
标题翻译：多处理器的多图像动态绑定和加载过程
公开(公告)号：US06684395B2
公开(公告)日：2004-01-27
申请号：US09753084
申请日：2000-12-28
申请人： Desmond R. Johnson , Donald F. Hooper , James D. Guilford
发明人： Desmond R. Johnson , Donald F. Hooper , James D. Guilford
IPC分类号： G06F944
CPC分类号： G06F9/44521
摘要： A method and mechanism for executing an application by a processor in a multi-processor configuration of processors, each having an associated instruction memory is presented. The application receives object code that includes an image for at least one other processor in the multi-processor configuration of processors. The application binds an import variable in the image to a parameter value and stores the image for the at least one other processor into the associated instruction memory.
摘要翻译：提出了一种用于在处理器的多处理器配置中由处理器执行应用的方法和机制，每个处理器具有相关联的指令存储器。该应用接收处理器的多处理器配置中的至少一个其他处理器的图像的目标代码。应用程序将图像中的导入变量绑定到参数值，并将至少一个其他处理器的映像存储到相关联的指令存储器中。

5. 发明授权

US06611276B1 Graphical user interface that displays operation of processor threads over time 有权
标题翻译：随时间显示处理器线程的操作的图形用户界面
公开(公告)号：US06611276B1
公开(公告)日：2003-08-26
申请号：US09386801
申请日：1999-08-31
申请人： Richard D. Muratori , Myles J. Wilde , Donald F. Hooper
发明人： Richard D. Muratori , Myles J. Wilde , Donald F. Hooper
IPC分类号： G06F300
CPC分类号： G06F11/3664 , G06F11/3404 , Y10S715/966
摘要： A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.
摘要翻译：图形用户界面（GUI）包括状态指示器，其显示在处理器的微引擎中运行的线程的执行状态。状态指示器将执行状态显示为处理器中时钟的功能。该GUI还包括显示对应于其中一个线程的计算机代码的窗口。

6. 发明授权

US07343563B2 Graphical user interface 有权
标题翻译：图形用户界面
公开(公告)号：US07343563B2
公开(公告)日：2008-03-11
申请号：US10612997
申请日：2003-07-02
申请人： Richard D. Muratori , Myles J. Wilde , Donald F. Hooper
发明人： Richard D. Muratori , Myles J. Wilde , Donald F. Hooper
IPC分类号： G06F3/00 , G06F3/14 , G06F13/00
CPC分类号： G06F11/3664 , G06F11/3404 , Y10S715/966
摘要： A graphical user interface (GUI) includes state indicators which show states of execution of threads running in microengines of a processor. The state indicators show the states of execution as functions of clocking in the processor. The GUI also includes a window showing computer code corresponding to one of the threads.
摘要翻译：图形用户界面（GUI）包括状态指示器，其显示在处理器的微引擎中运行的线程的执行状态。状态指示器将执行状态显示为处理器中时钟的功能。该GUI还包括显示对应于其中一个线程的计算机代码的窗口。

7. 发明授权

US07206858B2 DSL transmit traffic shaper structure and procedure 有权
标题翻译： DSL传输流量整形器结构和过程
公开(公告)号：US07206858B2
公开(公告)日：2007-04-17
申请号：US10247763
申请日：2002-09-19
申请人： Donald F. Hooper , Serge Kornfeld , Robert P. Ottavi , John C. Cole
发明人： Donald F. Hooper , Serge Kornfeld , Robert P. Ottavi , John C. Cole
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L47/522 , H04L47/22 , H04L47/50 , H04L47/527 , H04L47/568 , H04L2012/5665 , H04L2012/5681
摘要： A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.
摘要翻译：用于传输网络业务的方法和装置包括选择主环中的主节点，其中主节点对应于在主环中编码的第一传输机会。主节点指定代表虚拟端口的次环的次节点。该方法和装置还包括将网络流量发送到使用虚拟端口的虚拟连接。或者，传输网络流量涉及处理包括在调度环中编码的传输机会序列的调度，并且通过处理来自调度表的相应的第一最小数量的传输机会来满足调度的虚拟连接的最小数据速率，每个这样的传输机会由调度节点分配给调度的虚拟连接，其中调度节点被包括在调度环中。

8. 发明授权

US07991983B2 Register set used in multithreaded parallel processor architecture 有权
标题翻译：在多线程并行处理器架构中使用的寄存器集
公开(公告)号：US07991983B2
公开(公告)日：2011-08-02
申请号：US12477287
申请日：2009-06-03
申请人： Gilbert Wolrich , Matthew J Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/46 , G06F15/16
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
摘要翻译：一种基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器维护执行线程。执行线程访问组织成每个线程相对可寻址的多个相对可寻址的寄存器窗口的寄存器集。

9. 发明授权

US07421572B1 Branch instruction for processor with branching dependent on a specified bit in a register 失效
标题翻译：处理器的分支指令，取决于寄存器中指定的位
公开(公告)号：US07421572B1
公开(公告)日：2008-09-02
申请号：US10069195
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/32
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.
摘要翻译：描述诸如并行硬件的多线程处理器（12）之类的处理器。处理器（12）可以执行作为分支指令的计算机指令，其使处理器中的指令序列在设置或清零的寄存器（80,78,76b）的任何指定位上分支，并且指定哪个位指定的寄存器用作分支控制位。

10. 发明授权

US07240164B2 Folding for a multi-threaded network processor 有权
标题翻译：折叠为多线程网络处理器
公开(公告)号：US07240164B2
公开(公告)日：2007-07-03
申请号：US10642061
申请日：2003-08-14
申请人： Donald F. Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael F. Fallon , Sanjeev Jain , Myles J. Wilde , Gilbert M. Wolrich
发明人： Donald F. Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael F. Fallon , Sanjeev Jain , Myles J. Wilde , Gilbert M. Wolrich
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0842 , G06F12/0804
摘要： A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.
摘要翻译：使用不同的执行线程和存储器中的公共数据结构来处理与依赖数据流相关联的数据单元的机制。访问存储器中用于处理的公共数据结构使用单个读取操作和单个写入操作。以多个多线程处理阶段的方式折叠多个读 - 修改 - 写存储器操作包括控制第一级，其在与第二级相同的数据单元上操作以将上下文状态信息传递到第二级，用于一致性

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